Switch-level testability of the dynamic CMOS PLA

• Published in: Integration (Amsterdam) Vol. 9; no. 1; pp. 49 - 80
• Main Authors: Cockburn, B.F., Brzozowski, J.A.
• Format: Journal Article
• Language: English
• Published: Amsterdam Elsevier B.V 01.02.1990; Elsevier Science
• Subjects: Applied sciences; CMOS PLA; Electronics; Exact sciences and technology; fault modelling; Integrated circuits; Integrated circuits by function (including memories and processors); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Switch-level testability; testable PLA; Switch-level testability; testable PLA; fault modelling; CMOS PLA; VLSI circuit; Circuit design; Complementary MOS technology; Test; Integrated circuit; Programmable logic array; Boolean function; Reliability; Implementation; Defect detection
• ISSN: 0167-9260; 1872-7522
• DOI: 10.1016/0167-9260(90)90005-L

Functional testing, as opposed to parametric testing, plays an important role in testing VLSI integrated circuits. However, it appears that designs are not always carefully analysed in advance to determine precisely which faults are clean, i.e. testable by logic means alone. The programmable logic array (PLA) is a popular circuit form used to implement a system of Boolean functions over a set of input variables. This paper considers the testability of the dynamic CMOS PLA with respect to an extended switch-level fault model that includes node faults, transistor stuck-opens and stuck-ons, interconnect breaks, ohmic shorts, and crosspoint faults. Single occurrences of each fault in the fault model are classified as either clean, unclean, or clean subject to conditions on the products and output functions computed by the PLA. Finally, a modified dynamic CMOS PLA design is described and its improved switch-level testability properties are given.