High-Bandwidth and Energy-Efficient Memory Interfaces for the Data-Centric Era: Recent Advances, Design Challenges, and Future Prospects

• Published in: IEEE open journal of solid-state circuits Vol. 4; pp. 252 - 264
• Main Author: Chae, Joo-Hyung
• Format: Journal Article
• Language: English
• Published: IEEE 2024
• Subjects: Artificial intelligence; Artificial intelligence (AI); Bandwidth; dynamic random access memory (DRAM); Energy efficiency; high bandwidth; memory interface; Memory management; Optical signal processing; Random access memory
• ISSN: 2644-1349; 2644-1349
• DOI: 10.1109/OJSSCS.2024.3458900

Currently, we are living in a data-centric era as the need for large amounts of data has dramatically increased due to the widespread adoption of artificial intelligence (AI) in a variety of technology domains. In the current computing architecture, the memory input and output (I/O) bandwidth is becoming a bottleneck for improving computing performance; therefore, high-bandwidth memory interfaces are essential. In addition, the high power consumption of data centers to edge AI devices will lead to power shortages and climate crises in the near future; therefore, energy-efficient techniques for memory interfaces are also important. This article presents contemporary approaches to improve I/O bandwidth, such as increasing the I/O pin count and data rate/pin, and to save energy in memory interfaces. However, there are still some design challenges that require further improvements. Therefore, various design challenges and problems to be solved are discussed, and future perspectives, including chiplet and die-to-die interfaces, are presented. Based on various research and development efforts to overcome the current limitations, the technological paradigm shift and related industries are expected to advance to the next level.