NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 33; no. 12; pp. 1914 - 1927
• Main Authors: Hsu, Meng-Kai, Chen, Yi-Fang, Huang, Chau-Chin, Chou, Sheng, Lin, Tzu-Hen, Chen, Tung-Chieh, Chang, Yao-Wen
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2014; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithm design and analysis; Algorithms; Circuit design; Circuit synthesis; Congestion; Density; Design engineering; Design methodology; Hierarchies; Optimization; Placement; Routing; physical design; placement; Global routing; layouts
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2014.2360453

A wirelength-driven placer without considering routability could introduce irresolvable routing-congested placements. Therefore, it is desirable to develop an effective routability-driven placer for modern mixed-size designs employing hierarchical methodologies for faster turnaround time. In this paper, we propose a novel routability-driven analytical placement algorithm for hierarchical mixed-size circuit designs. This paper presents a novel design hierarchy identification technique to effectively identify design hierarchies and guide placement for better wirelength and routability. The proposed algorithm optimizes routability from four major aspects: 1) narrow channel handling; 2) pin density; 3) routing overflow optimization; and 4) net congestion optimization. Routability-driven legalization and detailed placement are also proposed to further optimize routing congestion. Compared with the participating teams for the 2012 ICCAD Design Hierarchy Aware Routability-driven Placement Contest, our placer can achieve the best quality (both the average overflow and wirelength) and the best overall score (by additionally considering running time).