Out-of-Order Parallel Discrete Event Simulation for Transaction Level Models

The validation of system models at the transaction-level typically relies on discrete event (DE) simulation. In order to reduce simulation time, parallel discrete event simulation (PDES) can be used by utilizing multiple cores available on today's host PCs. However, the total order of time impo...

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Published inIEEE transactions on computer-aided design of integrated circuits and systems Vol. 33; no. 12; pp. 1859 - 1872
Main Authors Weiwei Chen, Xu Han, Che-Wei Chang, Guantao Liu, Domer, Rainer
Format Journal Article
LanguageEnglish
Published New York IEEE 01.12.2014
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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ISSN0278-0070
1937-4151
DOI10.1109/TCAD.2014.2356469

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Abstract The validation of system models at the transaction-level typically relies on discrete event (DE) simulation. In order to reduce simulation time, parallel discrete event simulation (PDES) can be used by utilizing multiple cores available on today's host PCs. However, the total order of time imposed by regular DE simulators becomes a bottleneck that severely limits the benefits of parallel simulation. In this paper, we present a new out-of-order (OoO) PDES technique for simulating transaction-level models on multicore hosts. By localizing the simulation time to individual threads and carefully handling events at different times, a system model can be simulated following a partial order of time without loss of accuracy. Subject to advanced static analysis at compile time and table-based decisions at run time, threads can be issued early, reducing the idle time of available cores. Our proposed OoO PDES technique shows high performance gains in simulation speed with only a small increase in compile time. Using six embedded application examples, we also show the speed trade-off for multicore PDES based on different multithreading libraries.
AbstractList The validation of system models at the transaction-level typically relies on discrete event (DE) simulation. In order to reduce simulation time, parallel discrete event simulation (PDES) can be used by utilizing multiple cores available on today's host PCs. However, the total order of time imposed by regular DE simulators becomes a bottleneck that severely limits the benefits of parallel simulation. In this paper, we present a new out-of-order (OoO) PDES technique for simulating transaction-level models on multicore hosts. By localizing the simulation time to individual threads and carefully handling events at different times, a system model can be simulated following a partial order of time without loss of accuracy. Subject to advanced static analysis at compile time and table-based decisions at run time, threads can be issued early, reducing the idle time of available cores. Our proposed OoO PDES technique shows high performance gains in simulation speed with only a small increase in compile time. Using six embedded application examples, we also show the speed trade-off for multicore PDES based on different multithreading libraries.
Author Xu Han
Weiwei Chen
Domer, Rainer
Guantao Liu
Che-Wei Chang
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Issue 12
Keywords system-level description languages (SLDLs)
transaction level modeling
system-level design and validation
Parallel discrete event simulation (PDES)
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Snippet The validation of system models at the transaction-level typically relies on discrete event (DE) simulation. In order to reduce simulation time, parallel...
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SubjectTerms Accuracy
Computer aided design
Computer simulation
Design engineering
Discrete event simulation
Gain
Mathematical models
Multicore processing
Multithreading
Out of order
Parallel discrete event simulation (PDES)
Partial differential equations
Performance gain
Simulation
system-level description languages (SLDLs)
system-level design and validation
Tradeoffs
transaction level modeling
Transaction processing
Title Out-of-Order Parallel Discrete Event Simulation for Transaction Level Models
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