FPGA implementation of a full HD real-time HEVC main profile decoder

• Published in: IEEE transactions on consumer electronics Vol. 60; no. 3; pp. 476 - 484
• Main Authors: Engelhardt, Denis, Moller, Jan, Hahlbeck, Jan, Stabernack, Benno
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2014; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Coders; Coding; Coding standards; Context; Decoders; Decoding; Encoders; Field programmable gate arrays; FPGA; Hardware; hardware implementation; HEVC; Pipelines; Real time; Real-time systems; Syntactics; Transform coding; Video coding; video decoder
• ISSN: 0098-3063; 1558-4127
• DOI: 10.1109/TCE.2014.6937333

High Efficiency Video Coding (HEVC) is the newest video coding standard approved by the ISO/IEC and ITU-T in January 2013. By providing a video coding efficiency gain up to 50 % compared to H.264/MPEG-4 AVC high profile, the complexity of the used algorithms has raised significantly. Targeting video formats with higher spatial and temporal resolutions - e.g. 4Kp60 in broadcast applications - make implementing encoders and decoders a challenging task. A few software based implementations on DSPs and general purpose CPUs are known from the literature which suffer from real-time constraints, power dissipation and hardware costs of these systems. In this paper a pure hardware implementation of a Main Profile H.265/MPEG-HEVC Full HD capable decoder is presented solving both real-time and power constraints respectively. As a first implementation approach a state-of-the-art FPGA technology is chosen as a prototyping platform. This design can be used as a starting point for an ASIC implementation.