Capacitor Recombination Algorithm Combined with LMS Algorithm in 16-Bit SAR ADC with Redundancy

• Published in: Circuits, systems, and signal processing Vol. 42; no. 6; pp. 3181 - 3199
• Main Authors: Fan, Hua, Wang, Yunan, Wei, Qi, Feng, Quanyuan, Zhou, Wei
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.06.2023; Springer Nature B.V
• Subjects: Algorithms; Analog to digital converters; Calibration; Capacitors; Circuits and Systems; Convergence; Electrical Engineering; Electronics and Microelectronics; Engineering; Instrumentation; Monte Carlo simulation; Nonlinearity; Redundancy; Signal,Image and Speech Processing; Successive approximation register (SAR); Analog-to-digital converter (ADC); Least mean square (LMS) algorithm; Capacitor recombination algorithm
• ISSN: 0278-081X; 1531-5878
• DOI: 10.1007/s00034-022-02266-2

This paper presents a foreground calibration algorithm combination with a background calibration algorithm for successive approximation register analog-to-digital converters (ADC). The foreground calibration for capacitor mismatch is capacitor recombination algorithm and the background calibration for capacitor mismatch is single-channel least mean square (LMS) algorithm. The capacitor recombination algorithm can initially calibrate the capacitor array mismatch and provide an environment conducive to convergence for LMS algorithm. After running the capacitor recombination algorithm, the convergence speed of LMS algorithm can be improved. The results of 100 times of Monte Carlo simulation show that LMS algorithm can converge within 1500 cycles, the ADC signal-to-noise and distortion ratio is improved from 71.63 to 97.47 dB, the spurious-free dynamic range is improved from 84.98 to 125.28 dB, the effective number of bits is improved from 12.85 to 15.90 bits, the differential nonlinearity is reduced from 2.09 to 0.90 LSBs, and the integer nonlinear is reduced from 7.14 to 0.68 LSBs.