Capacitor Recombination Algorithm Combined with LMS Algorithm in 16-Bit SAR ADC with Redundancy
This paper presents a foreground calibration algorithm combination with a background calibration algorithm for successive approximation register analog-to-digital converters (ADC). The foreground calibration for capacitor mismatch is capacitor recombination algorithm and the background calibration f...
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| Published in | Circuits, systems, and signal processing Vol. 42; no. 6; pp. 3181 - 3199 |
|---|---|
| Main Authors | , , , , |
| Format | Journal Article |
| Language | English |
| Published |
New York
Springer US
01.06.2023
Springer Nature B.V |
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| Online Access | Get full text |
| ISSN | 0278-081X 1531-5878 |
| DOI | 10.1007/s00034-022-02266-2 |
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| Abstract | This paper presents a foreground calibration algorithm combination with a background calibration algorithm for successive approximation register analog-to-digital converters (ADC). The foreground calibration for capacitor mismatch is capacitor recombination algorithm and the background calibration for capacitor mismatch is single-channel least mean square (LMS) algorithm. The capacitor recombination algorithm can initially calibrate the capacitor array mismatch and provide an environment conducive to convergence for LMS algorithm. After running the capacitor recombination algorithm, the convergence speed of LMS algorithm can be improved. The results of 100 times of Monte Carlo simulation show that LMS algorithm can converge within 1500 cycles, the ADC signal-to-noise and distortion ratio is improved from 71.63 to 97.47 dB, the spurious-free dynamic range is improved from 84.98 to 125.28 dB, the effective number of bits is improved from 12.85 to 15.90 bits, the differential nonlinearity is reduced from 2.09 to 0.90 LSBs, and the integer nonlinear is reduced from 7.14 to 0.68 LSBs. |
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| AbstractList | This paper presents a foreground calibration algorithm combination with a background calibration algorithm for successive approximation register analog-to-digital converters (ADC). The foreground calibration for capacitor mismatch is capacitor recombination algorithm and the background calibration for capacitor mismatch is single-channel least mean square (LMS) algorithm. The capacitor recombination algorithm can initially calibrate the capacitor array mismatch and provide an environment conducive to convergence for LMS algorithm. After running the capacitor recombination algorithm, the convergence speed of LMS algorithm can be improved. The results of 100 times of Monte Carlo simulation show that LMS algorithm can converge within 1500 cycles, the ADC signal-to-noise and distortion ratio is improved from 71.63 to 97.47 dB, the spurious-free dynamic range is improved from 84.98 to 125.28 dB, the effective number of bits is improved from 12.85 to 15.90 bits, the differential nonlinearity is reduced from 2.09 to 0.90 LSBs, and the integer nonlinear is reduced from 7.14 to 0.68 LSBs. |
| Author | Fan, Hua Wei, Qi Feng, Quanyuan Zhou, Wei Wang, Yunan |
| Author_xml | – sequence: 1 givenname: Hua orcidid: 0000-0001-7629-2183 surname: Fan fullname: Fan, Hua email: fanhua7531@163.com organization: School of Integrated Circuit Science and Engineering (Exemplary School of Microelectronics), University of Electronic Science and Technology of China, Chongqing Institute of Microelectronics Industry Technology, University of Electronic Science and Technology of China – sequence: 2 givenname: Yunan surname: Wang fullname: Wang, Yunan organization: School of Shenzhen Institute for Advanced Study, University of Electronic Science and Technology of China – sequence: 3 givenname: Qi surname: Wei fullname: Wei, Qi email: weiqi@tsinghua.edu.cn organization: Department of Precision Instrument, Tsinghua University – sequence: 4 givenname: Quanyuan surname: Feng fullname: Feng, Quanyuan organization: School of Information Science and Technology, Southwest Jiaotong University – sequence: 5 givenname: Wei surname: Zhou fullname: Zhou, Wei organization: School of Integrated Circuit Science and Engineering (Exemplary School of Microelectronics), University of Electronic Science and Technology of China |
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| Cites_doi | 10.1109/ISCAS51556.2021.9401172 10.1109/ICICDT51558.2021.9626536 10.1109/ASICON52560.2021.9620474 10.23919/MIXDES.2018.8436826 10.1109/TCSI.2014.2354751 10.1109/ICICM54364.2021.9660322 10.1109/A-SSCC48613.2020.9336130 10.1109/JSSC.2019.2915583 10.1109/JSSC.2018.2793558 10.23919/VLSIC.2019.8777944 10.1109/ASSCC.2016.7844158 10.1109/JSSC.2016.2592623 10.1109/TCSI.2008.2001757 10.1109/VLSIC.2014.6858371 10.1109/ISSCC.2018.8310274 10.1109/TCSI.2021.3096242 10.1109/VLSI-DAT.2016.7482524 10.1109/ISSCC.2010.5433830 10.1109/JSSC.2005.856291 10.1109/JSSC.2017.2784761 10.1109/ISSCC.2010.5433829 10.1109/ISCAS.2013.6572376 10.1109/MWSCAS48704.2020.9184583 |
| ContentType | Journal Article |
| Copyright | The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. |
| Copyright_xml | – notice: The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. |
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| Keywords | Successive approximation register (SAR) Analog-to-digital converter (ADC) Least mean square (LMS) algorithm Capacitor recombination algorithm |
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| References | C.P. Hurrell, C. Lyden, D. Laing, D. Hummerston, M. Vickery, An 18b 12.5 MHz ADC with 93dB SNR, in: 2010 IEEE International Solid-State Circuits Conference-(ISSCC), pp. 378–379. IEEE (2010) A. Bannon, C.P. Hurrell, D. Hummerston, C. Lyden, An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range, in: 2014 Symposium on VLSI Circuits Digest of Technical Papers, pp. 1–2. IEEE (2014) Y.-S. Hu, J.-H. Lin, D.-G. Lin, K.-Y. Lin, H.-S. Chen, An 89.55dB-SFDR 179.6dB-FoMs 12-bit l-MS/s SAR-assisted SAR ADC with weight-split compensation calibration, in: 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 253–256 (2018) W.-H. Huang, S.-H. Wu, Z.-X. Chen, Y.-S. Shu, An amplifier-less calibration-free SAR ADC achieving 100dB SNDR for multi-channel ECG acquisition with 667mV pp linear input range, in: 2019 Symposium on VLSI Circuits, pp. C70–C71. IEEE (2019) B. Xu, Y. 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Fernando, A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOS, in: 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 153–156. IEEE (2016) X. Ding, K. Hofmann, L. Zhang, D. Yi, Y. Ma, Redundant double conversion based digital background calibration of SAR ADC with convergence acceleration and assistance, in: 2018 25th International Conference ”Mixed Design of Integrated Circuits and System” (MIXDES), pp. 192–197. IEEE (2018) McNeillJAMajidiRGongJ“Split ADC” background linearization of VCO-based ADCsIEEE Trans. Circuits Syst. I Regul. Pap.2014621495810.1109/TCSI.2014.2354751 2266_CR10 2266_CR21 2266_CR20 2266_CR12 2266_CR23 2266_CR11 2266_CR22 Y Zhou (2266_CR24) 2019; 54 JA McNeill (2266_CR17) 2014; 62 KL Chan (2266_CR2) 2008; 55 2266_CR7 2266_CR6 2266_CR9 2266_CR8 J Shen (2266_CR18) 2018; 53 Y-S Shu (2266_CR19) 2016; 51 2266_CR3 2266_CR14 2266_CR13 2266_CR5 J McNeill (2266_CR16) 2005; 40 2266_CR15 2266_CR1 B Chen (2266_CR4) 2018; 53 |
| References_xml | – reference: Y.-H. Chung, C.-H. Tien, Q.-F. Zeng, A 16-Bit calibration-free SAR ADC with binary-window and capacitor-swapping DAC switching schemes. IEEE Trans. Circuits Syst. I Regul. Pap. (2021) – reference: L. Wei, G. Shangshang, W. Xiao, S. Shiguang, Background LMS calibration algorithm realization for SAR-ADC, in: 2021 6th International Conference on Integrated Circuits and Microsystems (ICICM), pp. 142–146. IEEE (2021) – reference: M. Maddox, B. Chen, M. Coln, R. Kapusta, J. Shen, L. Fernando, A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOS, in: 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 153–156. IEEE (2016) – reference: McNeillJColnMCWLariveeBJ“Split ADC” architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADCIEEE J. Solid-State Circuits200540122437244510.1109/JSSC.2005.856291 – reference: Y. Wang, L. Zhang, F. Mei, Y. Chen, J. Wu, Digital calibration of capacitor mismatch and gain error in pipelined SAR ADCs, in: 2021 IEEE 14th International Conference on ASIC (ASICON), pp. 1–4. IEEE (2021) – reference: ShenJShikataAFernandoLDGuthrieNChenBMaddoxMMascarenhasNKapustaRColnMCWA 16-bit 16-MS/s SAR ADC with on-chip calibration in 55-nm CMOSIEEE J. Solid-State Circuits20185341149116010.1109/JSSC.2017.2784761 – reference: ChanKLRakuljicNGaltonISegmented dynamic element matching for high-resolution digital-to-analog conversionIEEE Trans. Circuits Syst. I Regul. Pap.2008551133833392251748510.1109/TCSI.2008.2001757 – reference: B. Xu, Y. Chiu, Background calibration of time-interleaved ADC using direct derivative information, in: 2013 IEEE International symposium on Circuits and Systems (ISCAS), pp. 2456–2459. IEEE (2013) – reference: K.-H. Chang, C.-C. Hsieh, A 12b 10MS/s 18.9 fJ/conversion-step sub-radix-2 SAR ADC, in: 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 1–4. IEEE (2016) – reference: Z. Lan, L. Dong, X. Jing, L. Geng, A 12-bit 100MS/s SAR ADC with digital error correction and high-speed LMS-based background calibration, in: 2021 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5. IEEE (2021) – reference: A. Bannon, C.P. Hurrell, D. Hummerston, C. Lyden, An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range, in: 2014 Symposium on VLSI Circuits Digest of Technical Papers, pp. 1–2. IEEE (2014) – reference: X. Ding, K. Hofmann, L. Zhang, D. Yi, Y. Ma, Redundant double conversion based digital background calibration of SAR ADC with convergence acceleration and assistance, in: 2018 25th International Conference ”Mixed Design of Integrated Circuits and System” (MIXDES), pp. 192–197. IEEE (2018) – reference: H. Li, M. Maddox, M.C.W. Coin, W. Buckley, D. Hummerston, N. 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Chiu, A 12b 22.5/45MS/s 3.0 mW 0.059 mm2\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$^{2}$$\end{document} CMOS SAR ADC achieving over 90dB SFDR, in: 2010 IEEE International Solid-State Circuits Conference-(ISSCC), pp. 380–381. IEEE (2010) – reference: McNeillJAMajidiRGongJ“Split ADC” background linearization of VCO-based ADCsIEEE Trans. Circuits Syst. I Regul. Pap.2014621495810.1109/TCSI.2014.2354751 – reference: F. Ye, J. Ren, A 12-bit SAR ADC using pseudo-dynamic weighting C-DAC for capacitor error calibration, in: 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 746–749 (2020) – reference: H. Fan, Y. Wang, X. Wu, A realizable digital bubble sorting SAR ADC calibration technology, in: 2021 International Conference on IC Design and Technology (ICICDT), pp. 1–4. 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| SubjectTerms | Algorithms Analog to digital converters Calibration Capacitors Circuits and Systems Convergence Electrical Engineering Electronics and Microelectronics Engineering Instrumentation Monte Carlo simulation Nonlinearity Redundancy Signal,Image and Speech Processing |
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| Title | Capacitor Recombination Algorithm Combined with LMS Algorithm in 16-Bit SAR ADC with Redundancy |
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