A hybrid hardware oriented motion estimation algorithm for HEVC/H.265

• Published in: Journal of real-time image processing Vol. 18; no. 3; pp. 953 - 966
• Main Authors: Gogoi, Sushanta, Peesapati, Rangababu
• Format: Journal Article
• Language: English
• Published: Berlin/Heidelberg Springer Berlin Heidelberg 01.06.2021; Springer Nature B.V
• Subjects: Achievement tests; Algorithms; Application specific integrated circuits; Coding; Coding standards; Computer architecture; Computer Graphics; Computer Science; Efficiency; Embedded systems; Field programmable gate arrays; Gate counting; Hardware; Image Processing and Computer Vision; Motion simulation; Multimedia Information Systems; Original Research Paper; Pattern Recognition; Power consumption; Quality standards; Signal,Image and Speech Processing; Smartphones; Standardization; Video compression; Integer Motion Estimation (IME); Field Programmable Gate Array (FPGA); Hardware architecture; High Efficiency Video Coding (HEVC)
• ISSN: 1861-8200; 1861-8219
• DOI: 10.1007/s11554-020-01056-w

High Efficiency Video Coding (HEVC) is the latest video coding standard that supports high resolution videos by providing approximately twice the compression efficiency as compared to its previous standard H.264. Motion Estimation (ME) in HEVC is the most computation-intensive block as a result it becomes a bottleneck in the design of the encoder while implementing video applications on various computing platforms such as general purpose and embedded processors. So developing computational efficient architectures on Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) platforms is inevitable. This paper proposes a fast hybrid search pattern algorithm and its hardware architecture for encoding UHD videos. The proposed Integer ME (IME) algorithm requires an average of 11.19% less encoding time than the default Test Zone Search (TZS) algorithm in HM reference software with compromising decrement in PSNR and increment in bit rate. The proposed architecture is implemented in both FPGA and ASIC platform with TSMC 90 nm technology library. It consumed 32-33% of resources in Virtex-7 FPGA and 2784.4 K equivalent gate count (in terms of NAND ) and 18 kB of memory, respectively. The results show that maximum frequency of the proposed architecture is 162 MHz and a total power consumption is 463.4 mW. The architecture provides a maximum throughput of 2.78 Gpixels/sec due to it process 32 × 32 CU comparatively much less clock cycles (59.5) as compared to the state-of-the-art literature . Further, it supports 8K UHD ( 8192 × 4320 ) @ 78 fps.