Highly accurate memristor modelling using MOS transistor for analog applications
Memristor technology has grown at a breakneck pace over the last decade, with the promise to transform data processing and storage. A memristor is a non-linear electrical component with two terminals that connect electric charge and magnetic flux. The ability to store and process data in the same ph...
Saved in:
Published in | Multimedia tools and applications Vol. 83; no. 25; pp. 66943 - 66958 |
---|---|
Main Authors | , |
Format | Journal Article |
Language | English |
Published |
New York
Springer US
01.07.2024
Springer Nature B.V |
Subjects | |
Online Access | Get full text |
ISSN | 1573-7721 1380-7501 1573-7721 |
DOI | 10.1007/s11042-023-18082-y |
Cover
Summary: | Memristor technology has grown at a breakneck pace over the last decade, with the promise to transform data processing and storage. A memristor is a non-linear electrical component with two terminals that connect electric charge and magnetic flux. The ability to store and process data in the same physical location is a fundamental benefit of memristors over traditional electrical components. It has a unique feature in that its resistance may be preset (resistor function) and then saved (memory function). Memristors, unlike other types of memory used in modern electronics, are stable and retain their state even if the device is turned off. In this work, a new highly accurate asymmetrical memristor is proposed for highly efficient analog applications. The proposed work used 5 Complementary metal–oxide–semiconductor (CMOS) devices in a parallel and series-connected manner. A bypass transistor is used to control the current flow between two terminals to perform a stable operation. A differential amplifier circuit is used to validate the proposed memristor performance. The proposed work is implemented using TSMC 45 nm CMOS technology. This application consumes less power and has good performance when compared with conventional techniques. In this work, a 1 V power supply occupies a 67.5 µm
2
layout area. The experimental results are improved when compared with the existing circuit. |
---|---|
Bibliography: | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 |
ISSN: | 1573-7721 1380-7501 1573-7721 |
DOI: | 10.1007/s11042-023-18082-y |