Data repair accelerating scheme for erasure-coded storage system based on FPGA and hierarchical parallel decoding structure

• Published in: Cluster computing Vol. 27; no. 6; pp. 7803 - 7823
• Main Authors: Chen, Junqi, Yang, Sijie, Wang, Yong, Ye, Miao, Lei, Fan
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.09.2024; Springer Nature B.V
• Subjects: Algorithms; Bandwidths; Codes; Coding; Columnar structure; Computer Communication Networks; Computer Science; Data loss; Data storage; Decoding; Efficiency; Fault tolerance; Field programmable gate arrays; Operating Systems; Processor Architectures; Repair; Source code; Storage systems; Structural reliability; Data repair; Erasure code; Fault-tolerant storage; FPGA; Hardware acceleration
• ISSN: 1386-7857; 1573-7543
• DOI: 10.1007/s10586-024-04401-x

Erasure coding has been widely used in commodity datacenter to tolerate faults, due to its ability to simultaneously provide high storage space utilization and data reliability. However, when data loss occurs, the extra data decoding and traffic overhead makes it difficult to improve their data repair efficiency, limiting their further application in the hot data storage systems. In this paper, we proposed an FPGA-based Data Repair accelerating scheme (FPGA-ECDR) for erasure-coded storage system, which employs the Cauchy Reed-Solomon(CRS) code, to overcome the aforementioned limitation. In FPGA-ECDR, multiple modules are designed to work collaboratively, enhancing the efficiency of data flow and ensuring the reliability of the data repair process. Then, a CRS decoding algorithm based on check matrix is used to reduce the complexity of matrix inversion in the decoding process, and hardware acceleration of the algorithm is realized by FPGA. Moreover, we proposed a Hierarchical Parallel Decoding Structure (HPDS) to optimize cache data reading timing and XOR logic operations in the decoding process. HPDS can effectively reduce the impact of Column Address Strobe (CAS) latency and improve repair efficiency. Finally, we conducted FPGA board-level verification of the proposed scheme, testing on CRS codes with different data sizes and parameters. The experimental results show that compared with the schemes of the current mainstream open-source erasure coding library Jerasure and Intel ISA-L acceleration library, as well as the Xilinx RS code decoding acceleration scheme based on the same FPGA platform, our proposed scheme has lower decoding latency and can improve the data decoding rate by 3.2 to 148.5 times and enhances the repair throughput by up to 21.4 times in fault-tolerant storage system.