Novel area-efficient and flexible architectures for optimal Ate pairing on FPGA

While FPGA is a suitable platform for implementing cryptographic algorithms, there are several challenges associated with implementing Optimal Ate pairing on FPGA, such as security, limited computing resources, and high power consumption. To overcome these issues, this study introduces three approac...

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Published inThe Journal of supercomputing Vol. 80; no. 2; pp. 2633 - 2659
Main Authors Azzouzi, Oussama, Anane, Mohamed, Koudil, Mouloud, Issad, Mohamed, Himeur, Yassine
Format Journal Article
LanguageEnglish
Published New York Springer US 01.01.2024
Springer Nature B.V
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Online AccessGet full text
ISSN0920-8542
1573-0484
DOI10.1007/s11227-023-05578-5

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Abstract While FPGA is a suitable platform for implementing cryptographic algorithms, there are several challenges associated with implementing Optimal Ate pairing on FPGA, such as security, limited computing resources, and high power consumption. To overcome these issues, this study introduces three approaches that can execute the optimal Ate pairing on Barreto–Naehrig curves using Jacobean coordinates with the goal of reaching 128-bit security on the Genesys board. The first approach is a pure software implementation utilizing the MicroBlaze processor. The second involves a combination of software and hardware, with key operations in F p and F p 2 being transformed into IP cores for the MicroBlaze. The third approach builds on the second by incorporating parallelism to improve the pairing process. The utilization of multiple MicroBlaze processors within a single system offers both versatility and parallelism to speed up pairing calculations. A variety of methods and parameters are used to optimize the pairing computation, including Montgomery modular multiplication, the Karatsuba method, Jacobean coordinates, the Complex squaring method, sparse multiplication, squaring in G ϕ 6 F p 12 , and the addition chain method. The proposed systems are designed to efficiently utilize limited resources in restricted environments, while still completing tasks in a timely manner.
AbstractList While FPGA is a suitable platform for implementing cryptographic algorithms, there are several challenges associated with implementing Optimal Ate pairing on FPGA, such as security, limited computing resources, and high power consumption. To overcome these issues, this study introduces three approaches that can execute the optimal Ate pairing on Barreto–Naehrig curves using Jacobean coordinates with the goal of reaching 128-bit security on the Genesys board. The first approach is a pure software implementation utilizing the MicroBlaze processor. The second involves a combination of software and hardware, with key operations in F p and F p 2 being transformed into IP cores for the MicroBlaze. The third approach builds on the second by incorporating parallelism to improve the pairing process. The utilization of multiple MicroBlaze processors within a single system offers both versatility and parallelism to speed up pairing calculations. A variety of methods and parameters are used to optimize the pairing computation, including Montgomery modular multiplication, the Karatsuba method, Jacobean coordinates, the Complex squaring method, sparse multiplication, squaring in G ϕ 6 F p 12 , and the addition chain method. The proposed systems are designed to efficiently utilize limited resources in restricted environments, while still completing tasks in a timely manner.
While FPGA is a suitable platform for implementing cryptographic algorithms, there are several challenges associated with implementing Optimal Ate pairing on FPGA, such as security, limited computing resources, and high power consumption. To overcome these issues, this study introduces three approaches that can execute the optimal Ate pairing on Barreto–Naehrig curves using Jacobean coordinates with the goal of reaching 128-bit security on the Genesys board. The first approach is a pure software implementation utilizing the MicroBlaze processor. The second involves a combination of software and hardware, with key operations in Fp and Fp2 being transformed into IP cores for the MicroBlaze. The third approach builds on the second by incorporating parallelism to improve the pairing process. The utilization of multiple MicroBlaze processors within a single system offers both versatility and parallelism to speed up pairing calculations. A variety of methods and parameters are used to optimize the pairing computation, including Montgomery modular multiplication, the Karatsuba method, Jacobean coordinates, the Complex squaring method, sparse multiplication, squaring in Gϕ6Fp12, and the addition chain method. The proposed systems are designed to efficiently utilize limited resources in restricted environments, while still completing tasks in a timely manner.
Author Issad, Mohamed
Azzouzi, Oussama
Koudil, Mouloud
Himeur, Yassine
Anane, Mohamed
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Keywords Montgomery modular multiplication
Optimal Ate pairing
Flexible architecture
Virtex-5
Karatsuba method
MicroBlaze
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Snippet While FPGA is a suitable platform for implementing cryptographic algorithms, there are several challenges associated with implementing Optimal Ate pairing on...
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SubjectTerms Algorithms
Compilers
Computer Science
Confidentiality
Cryptography
Design
Digital signatures
Edge computing
Efficiency
Error correction & detection
Field programmable gate arrays
Interpreters
Microprocessors
Multiplication
Multiplication & division
Number systems
Optimization
Parallel processing
Processor Architectures
Programming Languages
Quantum computing
Security
Software
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Title Novel area-efficient and flexible architectures for optimal Ate pairing on FPGA
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