A Deep-Unfolding-Optimized Coordinate-Descent Data-Detector ASIC for mmWave Massive MIMO

• Published in: IEEE journal on selected areas in communications Vol. 43; no. 4; pp. 1323 - 1338
• Main Authors: Li, Zixiao, Hadi Mirfarshbafan, Seyed, Castaneda, Oscar, Studer, Christoph
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2025; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Antennas; Application specific integrated circuits; Application-specific integrated circuit (ASIC); block coordinate descent; Channels; Complexity theory; Computer architecture; data detection; Data transmission; deep unfolding; Detectors; massive multiple-input multiple-output (MIMO); millimeter wave; Millimeter wave communication; Millimeter waves; MIMO communication; OFDM; Orthogonal Frequency Division Multiplexing; orthogonal frequency-division multiplexing (OFDM); Sensors; soft output; Symbols; Throughput; Vectors; Very large scale integration
• ISSN: 0733-8716; 1558-0008
• DOI: 10.1109/JSAC.2025.3531558

We present a 22nm FD-SOI (fully depleted silicon-on-insulator) application-specific integrated circuit (ASIC) implementation of a novel soft-output Gram-domain block coordinate descent (GBCD) data detector for massive multi-user (MU) multiple-input multiple-output (MIMO) systems. The ASIC simultaneously addresses the high throughput requirements for millimeter wave (mmWave) communication, stringent area and power budget per subcarrier in an orthogonal frequency-division multiplexing (OFDM) system, and error-rate performance challenges posed by realistic mmWave channels. The proposed GBCD algorithm utilizes a posterior mean estimate (PME) denoiser and is optimized using deep unfolding, which results in superior error-rate performance even in scenarios with highly correlated channels or where the number of user equipment (UE) data streams is comparable to the number of basestation (BS) antennas. The fabricated GBCD ASIC supports up to 16 UEs transmitting QPSK to 256-QAM symbols to a 128-antenna BS, and achieves a peak throughput of 7.1Gbps at 367mW. The core area is only 0.97mm2 thanks to a reconfigurable array of processing elements that enables extensive resource sharing. Measurement results demonstrate that the proposed GBCD data-detector ASIC achieves best-in-class throughput and area efficiency.