PSO with aging leader and challengers for optimal design of high speed symmetric switching CMOS inverter
It is the general law of nature that every organism in the earth ages and has a limited lifespan. With the passage of time, the leader of the colony becomes old and feeble. This old leader no longer has the capability to lead the colony unless or otherwise it is challenged by a new and young challen...
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          | Published in | International journal of machine learning and cybernetics Vol. 8; no. 4; pp. 1403 - 1422 | 
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| Main Authors | , , , | 
| Format | Journal Article | 
| Language | English | 
| Published | 
        Berlin/Heidelberg
          Springer Berlin Heidelberg
    
        01.08.2017
     Springer Nature B.V  | 
| Subjects | |
| Online Access | Get full text | 
| ISSN | 1868-8071 1868-808X  | 
| DOI | 10.1007/s13042-016-0517-z | 
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| Summary: | It is the general law of nature that every organism in the earth ages and has a limited lifespan. With the passage of time, the leader of the colony becomes old and feeble. This old leader no longer has the capability to lead the colony unless or otherwise it is challenged by a new and young challenger with great deal of enthusiasm. Thus, aging provides opportunities for the other individuals of the colony to challenge the leadership capability of the leader. This natural aging mechanism of the organism has been modelled into particle swarm optimization (PSO) and termed as PSO with aging leader and challenger (ALC-PSO). The main objective of this paper is to efficiently design a high speed symmetric switching CMOS inverter. Here, ALC-PSO is used for the optimal symmetric switching characterization of CMOS inverter. The optimal symmetric switching characterization of ALC-PSO is compared with those of real coded genetic algorithm (RGA), and conventional PSO reported in the recent literature. ALC-PSO based design results are also compared with the SPICE based results. Extensive simulation results justify the superior optimization capability of ALC-PSO over the afore-mentioned optimization techniques for the examples considered and can be efficiently used for optimal CMOS inverter design. | 
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| Bibliography: | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14  | 
| ISSN: | 1868-8071 1868-808X  | 
| DOI: | 10.1007/s13042-016-0517-z |