Clock auto-synchronization method for BESIII ETOF upgrade

An automatic clock synchronization method implemented in a field programmable gate array （FPGA） is proposed in this paper. It is developed for the clock system which will be applied in the end-cap time of flight （ETOF） upgrade of the Beijing Spectrometer （BESIII）. In this design, an FPGA is used to...

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Bibliographic Details
Published inChinese physics C Vol. 39; no. 12; pp. 57 - 61
Main Author 王思宇 曹平 刘树彬 安琪
Format Journal Article
LanguageEnglish
Published 01.12.2015
Subjects
Automation
Circuit design
Clock synchronization
Clock systems
Clocks
Field programmable gate arrays
FPGA
Synchronism
Synchronization
信号处理电路
可调谐
同步方法
时钟系统
滤光器
现场可编程门阵列
电子
Online AccessGet full text
ISSN1674-1137
0254-3052
DOI10.1088/1674-1137/39/12/126102

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Summary:An automatic clock synchronization method implemented in a field programmable gate array （FPGA） is proposed in this paper. It is developed for the clock system which will be applied in the end-cap time of flight （ETOF） upgrade of the Beijing Spectrometer （BESIII）. In this design, an FPGA is used to automatically monitor the synchronization circuit and deal with signals coming from the external clock synchronization circuit. By testing different delay time of the detection signal and analyzing the signal state returned~ the synchronization windows can be found automatically by the FPGA. The new clock system not only retains low clock jitter which is less than 20ps root mean square （RMS）, but also demonstrates automatic synchronization to the beam bunches. So far, the clock auto-synchronizing function has been working successfully under a series of tests. It will greatly simplify the system initialization and maintenance in the future.
Bibliography:BESIII, endcap time-of-flight, clock synchronization
11-5641/O4
An automatic clock synchronization method implemented in a field programmable gate array （FPGA） is proposed in this paper. It is developed for the clock system which will be applied in the end-cap time of flight （ETOF） upgrade of the Beijing Spectrometer （BESIII）. In this design, an FPGA is used to automatically monitor the synchronization circuit and deal with signals coming from the external clock synchronization circuit. By testing different delay time of the detection signal and analyzing the signal state returned~ the synchronization windows can be found automatically by the FPGA. The new clock system not only retains low clock jitter which is less than 20ps root mean square （RMS）, but also demonstrates automatic synchronization to the beam bunches. So far, the clock auto-synchronizing function has been working successfully under a series of tests. It will greatly simplify the system initialization and maintenance in the future.
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ISSN:1674-1137
0254-3052
DOI:10.1088/1674-1137/39/12/126102