TOT measurement implemented in FPGA TDC

• Published in: Chinese physics C Vol. 39; no. 11; pp. 60 - 64
• Main Author: 范欢欢 曹平 刘树彬 安琪
• Format: Journal Article
• Language: English
• Published: 01.11.2015
• Subjects: Channels; Clocks; Electronics; Field programmable gate arrays; FPGA实现; Integrity; Intervals; Specifications; TDCS; Time measurement; TOT; Xilinx; 时间数字转换器; 时间测量方法; 现场可编程门阵列; 高能物理实验
• ISSN: 1674-1137; 0254-3052
• DOI: 10.1088/1674-1137/39/11/116101

Time measurement plays a crucial role for the purpose of particle identification in high energy physics experiments. With increasingly demanding physics goals and the development of electronics, modern time measurement systems need to meet the requirement of excellent resolution specification as well as high integrity. Based on Field Programmable Gate Arrays（FPGAs）, FPGA time-to-digital converters（TDCs） have become one of the most mature and prominent time measurement methods in recent years. For correcting the time-walk effect caused by leading timing, a time-over-threshold（TOT） measurement should be added to the FPGA TDC. TOT can be obtained by measuring the interval between the signal leading and trailing edges. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels need to be used at the same time, one for leading, the other for trailing. However, this method unavoidably increases the amount of FPGA resources used and reduces the TDC＇s integrity.This paper presents one method of TOT measurement implemented in a Xilinx Virtex-5 FPGA. In this method,TOT measurement can be achieved using only one TDC input channel. The consumed resources and time resolution can both be guaranteed. Testing shows that this TDC can achieve resolution better than 15 ps for leading edge measurement and 37 ps for TOT measurement. Furthermore, the TDC measurement dead time is about two clock cycles, which makes it good for applications with higher physics event rates.