ESD performance of LDMOS with source-bulk layout structure optimization

To enhance the robustness of LDMOS ESD protection devices, the influence of a source-bulk layout structure is analyzed by theoretical analysis and numerical simulation. Novel structures with varied source-bulk layout structures are fabricated and compared. As demonstrated by TLP testing, the optimiz...

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Bibliographic Details
Published inJournal of semiconductors Vol. 34; no. 12; pp. 40 - 44
Main Author 蒋苓利 樊航 林丽娟 张波
Format Journal Article
LanguageEnglish
Published 01.12.2013
Subjects
Computer simulation
Devices
Electrostatic discharges
ESD保护器件
LDMOS器件
Mathematical models
Optimization
Robustness
Semiconductors
布局结构
性能
散装
数值模拟分析
结构优化
鲁棒性
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ISSN1674-4926
DOI10.1088/1674-4926/34/12/124003

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Summary:To enhance the robustness of LDMOS ESD protection devices, the influence of a source-bulk layout structure is analyzed by theoretical analysis and numerical simulation. Novel structures with varied source-bulk layout structures are fabricated and compared. As demonstrated by TLP testing, the optimized structure has an 88% larger It2 than a conventional one, and its Vtl is reduced from 55.53 to 50.69 V.
Bibliography:To enhance the robustness of LDMOS ESD protection devices, the influence of a source-bulk layout structure is analyzed by theoretical analysis and numerical simulation. Novel structures with varied source-bulk layout structures are fabricated and compared. As demonstrated by TLP testing, the optimized structure has an 88% larger It2 than a conventional one, and its Vtl is reduced from 55.53 to 50.69 V.
11-5781/TN
Jiang Lingli,Fan Hang, Lin Lijuan, Zhang Bo（State Key Laboratory of Electronic Thin Film and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China）
ESD; LDMOS; source-bulk layout structure
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ISSN:1674-4926
DOI:10.1088/1674-4926/34/12/124003