ONLINE SCHEDULING AND PLACEMENT OF HARDWARE MODULES ON PARTIALLY DYNAMIC ARCHITECTURES

• Published in: Journal of circuits, systems, and computers Vol. 22; no. 3; p. 1350005
• Main Authors: OUNI, BOURAOUI, MTIBAA, ABDELLATIF
• Format: Journal Article
• Language: English
• Published: Singapore World Scientific Publishing Company 01.03.2013; World Scientific Publishing Co. Pte., Ltd
• Subjects: Algorithms; Changing environments; Design optimization; Field programmable gate arrays; Modules; Optimization algorithms; Placement; Reconfiguration; Scheduling; Temporal placement; run-time reconfigured systems; run-time partial reconfiguration; temporal placement algorithm
• ISSN: 0218-1266; 1793-6454
• DOI: 10.1142/S0218126613500059

New FPGA families can be reconfigured partially, meaning that only a certain portion of the chip area is reprogrammed. Partial reconfiguration makes possible to exchange function blocks on the FPGA and adapt it to a changing environment. It is used to have only a subset of necessary applications running on chip at each time, and replacing them by those needed. One of the challenging problems is the scheduling and the placement of modules on reconfigurable resources, this problem is called temporal placement. Several modules placement techniques have been introduced in the literature to solve the temporal placement problem. In this paper, we examine the temporal placement, showing how it can be decomposed into a number of distinct but not independent subtasks. Furthermore, in this paper, we have classified the temporal placement algorithms into the following classes: (1) Algorithms without design optimization (2) Routing cost optimization algorithms (3) Reconfiguration time optimization algorithms (4) Modules interfering optimization algorithms (5) Device resources optimization algorithms After that, experiments are conducted in order to evaluate the complexity and performances in term of traditional design metrics, like latency, area, etc., of each algorithm.