High-Performance Implementation of Wideband Coherent Signal-Subspace (CSS)-Based DOA Algorithm on FPGA

Coherent Signal-Subspace (CSS) is a technique to separate the wide frequency band into narrowband components which can be applied in many applications such as smart antennas for wireless communications and radar. However, CSS is computationally intensive and may not achieve the real-time requirement...

Full description

Saved in:
Bibliographic Details
Published inJournal of circuits, systems, and computers Vol. 30; no. 11; p. 2150196
Main Authors Jarrah, Amin, Almomany, Abedalmuhdi, Alsobeh, Anas M. R., Alqudah, Eman
Format Journal Article
LanguageEnglish
Published Singapore World Scientific Publishing Company 15.09.2021
World Scientific Publishing Co. Pte., Ltd
Subjects
Online AccessGet full text
ISSN0218-1266
1793-6454
DOI10.1142/S0218126621501966

Cover

Abstract Coherent Signal-Subspace (CSS) is a technique to separate the wide frequency band into narrowband components which can be applied in many applications such as smart antennas for wireless communications and radar. However, CSS is computationally intensive and may not achieve the real-time requirement. Therefore, this work aims to propose an efficient implementation of the CSS method on Field-Programmable Gate Array (FPGA) to achieve the desired performance. Different parallelization and optimization techniques such as loop unrolling, loop pipelining, dataflow, and loop flattening are adopted and applied to explore the opportunities of any computation and storage that could be eliminated in order to achieve high efficiency. The results of the proposed optimized implementation achieve the highest performance compared with other related implementations.
AbstractList Coherent Signal-Subspace (CSS) is a technique to separate the wide frequency band into narrowband components which can be applied in many applications such as smart antennas for wireless communications and radar. However, CSS is computationally intensive and may not achieve the real-time requirement. Therefore, this work aims to propose an efficient implementation of the CSS method on Field-Programmable Gate Array (FPGA) to achieve the desired performance. Different parallelization and optimization techniques such as loop unrolling, loop pipelining, dataflow, and loop flattening are adopted and applied to explore the opportunities of any computation and storage that could be eliminated in order to achieve high efficiency. The results of the proposed optimized implementation achieve the highest performance compared with other related implementations.
Author Almomany, Abedalmuhdi
Alsobeh, Anas M. R.
Jarrah, Amin
Alqudah, Eman
Author_xml – sequence: 1
  givenname: Amin
  surname: Jarrah
  fullname: Jarrah, Amin
– sequence: 2
  givenname: Abedalmuhdi
  surname: Almomany
  fullname: Almomany, Abedalmuhdi
– sequence: 3
  givenname: Anas M. R.
  surname: Alsobeh
  fullname: Alsobeh, Anas M. R.
– sequence: 4
  givenname: Eman
  surname: Alqudah
  fullname: Alqudah, Eman
BookMark eNp9kE1LxDAQhoMouK7-AG8FL3qoZpI0bY91_VhhYReqeCxpPnYjbbMmXcR_b5eKBwVPc3jneWd4TtBh5zqN0DngawBGbkpMIAPCOYEEQ875AZpAmtOYs4Qdosk-jvf5MToJ4Q1jzJIMT5CZ2_UmXmlvnG9FJ3X01G4b3equF711XeRM9GqVrkWnopnbaD8kUWnXnWjicleHrRiYy1lZXsW3ImgV3S2LqGjWztt-00ZDw8PqsThFR0Y0QZ99zyl6ebh_ns3jxfLxaVYsYkmB8VjIWoFJSI0BaAZUS80oTwykaZbRHBOZ59SA0pRkmMoaaylVIhhWUkmdMjpFF2Pv1rv3nQ599eZ2fvg1VCRJOcOE0_0WjFvSuxC8NtXW21b4zwpwtddZ_dE5MOkvRtpRUe-Fbf4l8Uh-ON-oIO1g0Borf47-Rb4AHECIWQ
CitedBy_id crossref_primary_10_2174_1573409919666230503094411
crossref_primary_10_1007_s42835_023_01432_z
crossref_primary_10_1371_journal_pone_0301720
crossref_primary_10_1371_journal_pone_0302578
crossref_primary_10_30935_ojcmt_14196
crossref_primary_10_1016_j_jksuci_2022_04_006
Cites_doi 10.1145/321021.321030
10.1109/TAC.1974.1100705
10.1109/TSP.2012.2231676
10.4108/ICST.CROWNCOM2010.9283
10.1109/MC.2008.65
10.1093/imanum/drq003
10.1007/s00453-006-1219-9
10.1093/comjnl/6.1.99
10.1137/1.9781611971446
10.1016/j.parco.2018.10.003
10.1007/978-1-4471-6395-4
10.1109/RADAR.2010.5494559
10.1145/1198555.1198767
10.1109/ACSSC.2011.6190383
10.1109/TCAD.2019.2943570
10.1016/j.parco.2008.12.007
10.1155/2009/219140
10.1109/ACSSC.2011.6190390
10.1137/1.9780898717808
10.2307/2004005
10.1007/978-3-662-00551-4_4
10.1109/PAAP.2014.70
10.1142/7767
10.1145/307418.307520
10.1016/0165-1684(90)90158-U
10.1007/BF02241222
10.1063/1.3466798
10.1109/78.747802
10.1109/RADAR.2007.374263
10.1109/78.286954
10.1145/320941.320947
ContentType Journal Article
Copyright 2021, World Scientific Publishing Company
2021. World Scientific Publishing Company
Copyright_xml – notice: 2021, World Scientific Publishing Company
– notice: 2021. World Scientific Publishing Company
DBID AAYXX
CITATION
DOI 10.1142/S0218126621501966
DatabaseName CrossRef
DatabaseTitle CrossRef
DatabaseTitleList
CrossRef

DeliveryMethod fulltext_linktorsrc
Discipline Engineering
EISSN 1793-6454
ExternalDocumentID 10_1142_S0218126621501966
S0218126621501966
GroupedDBID .DC
0R~
4.4
5GY
ADSJI
AENEX
ALMA_UNASSIGNED_HOLDINGS
CS3
DU5
EBS
HZ~
O9-
P2P
P71
RWJ
WSC
AAYXX
ADMLS
CITATION
ID FETCH-LOGICAL-c3146-acbd1f52b0113813ece4365f177883902c993f1de32803cb0eccd5a40dcdce743
ISSN 0218-1266
IngestDate Sun Jun 29 16:00:58 EDT 2025
Tue Jul 01 03:09:44 EDT 2025
Thu Apr 24 23:04:35 EDT 2025
Fri Aug 23 08:20:05 EDT 2024
IsPeerReviewed true
IsScholarly true
Issue 11
Keywords High performance
FPGA
signal processing
parallel architecture and optimization
Language English
LinkModel OpenURL
MergedId FETCHMERGED-LOGICAL-c3146-acbd1f52b0113813ece4365f177883902c993f1de32803cb0eccd5a40dcdce743
Notes This paper was recommended by Regional Editor Tongquan Wei.
ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ORCID 0000-0001-8039-190X
PQID 2576402634
PQPubID 2049873
ParticipantIDs worldscientific_primary_S0218126621501966
crossref_citationtrail_10_1142_S0218126621501966
crossref_primary_10_1142_S0218126621501966
proquest_journals_2576402634
ProviderPackageCode CITATION
AAYXX
PublicationCentury 2000
PublicationDate 20210915
PublicationDateYYYYMMDD 2021-09-15
PublicationDate_xml – month: 09
  year: 2021
  text: 20210915
  day: 15
PublicationDecade 2020
PublicationPlace Singapore
PublicationPlace_xml – name: Singapore
PublicationTitle Journal of circuits, systems, and computers
PublicationYear 2021
Publisher World Scientific Publishing Company
World Scientific Publishing Co. Pte., Ltd
Publisher_xml – name: World Scientific Publishing Company
– name: World Scientific Publishing Co. Pte., Ltd
References S0218126621501966BIB006
S0218126621501966BIB028
S0218126621501966BIB007
S0218126621501966BIB029
S0218126621501966BIB004
S0218126621501966BIB026
S0218126621501966BIB005
S0218126621501966BIB008
S0218126621501966BIB009
S0218126621501966BIB042
Li M. (S0218126621501966BIB001) 2013; 3
S0218126621501966BIB043
S0218126621501966BIB040
S0218126621501966BIB041
Grout I. (S0218126621501966BIB011) 2011
S0218126621501966BIB003
S0218126621501966BIB025
Bai J. (S0218126621501966BIB030) 2011; 12
S0218126621501966BIB044
S0218126621501966BIB023
S0218126621501966BIB045
S0218126621501966BIB039
S0218126621501966BIB015
S0218126621501966BIB016
S0218126621501966BIB019
Ghosh D. (S0218126621501966BIB021) 2012
Press W. H. (S0218126621501966BIB038) 2007
S0218126621501966BIB010
S0218126621501966BIB032
S0218126621501966BIB013
S0218126621501966BIB035
S0218126621501966BIB014
S0218126621501966BIB036
S0218126621501966BIB033
S0218126621501966BIB012
S0218126621501966BIB034
Cipra B. A. (S0218126621501966BIB037) 2000; 33
Worner S. (S0218126621501966BIB017) 2008
Gonzalez R. C. (S0218126621501966BIB018) 2004
Majid M. W. (S0218126621501966BIB024) 2014; 2
References_xml – ident: S0218126621501966BIB036
  doi: 10.1145/321021.321030
– ident: S0218126621501966BIB045
  doi: 10.1109/TAC.1974.1100705
– ident: S0218126621501966BIB004
  doi: 10.1109/TSP.2012.2231676
– ident: S0218126621501966BIB026
  doi: 10.4108/ICST.CROWNCOM2010.9283
– ident: S0218126621501966BIB012
  doi: 10.1109/MC.2008.65
– volume-title: Digital Systems Design with FPGAs and CPLDs
  year: 2011
  ident: S0218126621501966BIB011
– ident: S0218126621501966BIB042
  doi: 10.1093/imanum/drq003
– start-page: 1
  volume-title: Proc. Numerical Analysis Seminar
  year: 2008
  ident: S0218126621501966BIB017
– volume-title: Numerical Recipes: The Art of Scientific Computing
  year: 2007
  ident: S0218126621501966BIB038
– ident: S0218126621501966BIB032
  doi: 10.1007/s00453-006-1219-9
– ident: S0218126621501966BIB040
  doi: 10.1093/comjnl/6.1.99
– ident: S0218126621501966BIB039
  doi: 10.1137/1.9781611971446
– ident: S0218126621501966BIB044
  doi: 10.1016/j.parco.2018.10.003
– volume: 3
  start-page: 1000173
  year: 2013
  ident: S0218126621501966BIB001
  publication-title: J. Electr. Electron. Syst.
– ident: S0218126621501966BIB019
  doi: 10.1007/978-1-4471-6395-4
– ident: S0218126621501966BIB005
  doi: 10.1109/RADAR.2010.5494559
– ident: S0218126621501966BIB010
  doi: 10.1145/1198555.1198767
– ident: S0218126621501966BIB003
  doi: 10.1109/ACSSC.2011.6190383
– volume: 2
  start-page: 29
  year: 2014
  ident: S0218126621501966BIB024
  publication-title: Sci. J. Circuits Syst. Signal Process.
– ident: S0218126621501966BIB014
  doi: 10.1109/TCAD.2019.2943570
– volume-title: Digital Image Processing Using MATLAB
  year: 2004
  ident: S0218126621501966BIB018
– ident: S0218126621501966BIB025
  doi: 10.1016/j.parco.2008.12.007
– ident: S0218126621501966BIB028
  doi: 10.1155/2009/219140
– ident: S0218126621501966BIB006
  doi: 10.1109/ACSSC.2011.6190390
– year: 2012
  ident: S0218126621501966BIB021
  publication-title: Int. J. Adv. Innov. Thoughts Ideas
– volume: 33
  start-page: 1
  year: 2000
  ident: S0218126621501966BIB037
  publication-title: SIAM News
– ident: S0218126621501966BIB041
  doi: 10.1137/1.9780898717808
– volume: 12
  start-page: 199
  year: 2011
  ident: S0218126621501966BIB030
  publication-title: Ann. Econ. Finance
– ident: S0218126621501966BIB035
  doi: 10.2307/2004005
– ident: S0218126621501966BIB016
  doi: 10.1007/978-3-662-00551-4_4
– ident: S0218126621501966BIB029
  doi: 10.1109/PAAP.2014.70
– ident: S0218126621501966BIB009
  doi: 10.1142/7767
– ident: S0218126621501966BIB013
  doi: 10.1145/307418.307520
– ident: S0218126621501966BIB015
  doi: 10.1016/0165-1684(90)90158-U
– ident: S0218126621501966BIB043
  doi: 10.1007/BF02241222
– ident: S0218126621501966BIB034
  doi: 10.1063/1.3466798
– ident: S0218126621501966BIB023
  doi: 10.1109/78.747802
– ident: S0218126621501966BIB008
  doi: 10.1109/RADAR.2007.374263
– ident: S0218126621501966BIB007
  doi: 10.1109/78.286954
– ident: S0218126621501966BIB033
  doi: 10.1145/320941.320947
SSID ssj0004580
Score 2.273057
Snippet Coherent Signal-Subspace (CSS) is a technique to separate the wide frequency band into narrowband components which can be applied in many applications such as...
SourceID proquest
crossref
worldscientific
SourceType Aggregation Database
Enrichment Source
Index Database
Publisher
StartPage 2150196
SubjectTerms Algorithms
Field programmable gate arrays
Frequencies
Narrowband
Optimization
Optimization techniques
Parallel processing
Wireless communications
Title High-Performance Implementation of Wideband Coherent Signal-Subspace (CSS)-Based DOA Algorithm on FPGA
URI http://www.worldscientific.com/doi/abs/10.1142/S0218126621501966
https://www.proquest.com/docview/2576402634
Volume 30
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
journalDatabaseRights – providerCode: PRVEBS
  databaseName: Inspec with Full Text
  customDbUrl:
  eissn: 1793-6454
  dateEnd: 20241102
  omitProxy: false
  ssIdentifier: ssj0004580
  issn: 0218-1266
  databaseCode: ADMLS
  dateStart: 19910301
  isFulltext: true
  titleUrlDefault: https://www.ebsco.com/products/research-databases/inspec-full-text
  providerName: EBSCOhost
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwnV1bb9MwFLZK9wIPE1fRMZAfQGJULomTOOljGBsTomiim9hbFV-yRWoaaNMXfhc_kOPYTdLLEOMlqpL4pO335fizfc4xQq8TeM245AlxeECJ74YeiSQMViIAP_QYZ2mks5FHX9nZpf_5KrjqdH63opaWJR-IXzvzSv4HVTgHuOos2TsgWxuFE_AZ8IUjIAzHf8JYB2mQ81bof1XrN7fpRJUQ_J5JxfXkuM7DqCoxjbNrMEy0x4DxciUxj8fjN3RIPkCPJvswWuzH0-tinpU3uV5LOD3_FN-iYUU2F8usrLhgakIvVuGgwm4X0YQoJnNwbJUvyrOakvE0L-C7V1DHXMlkmi9vZNZcXhRcmVazZNEfDfrfBs3Fn0tpTJ7kluV2AoO6OtrCpHBaPwcqg7iU2YrYxg-D2yC62FjbUdsFHEtId83tBrrOz-4uwafVonSlZRizt-4ov73RLdbBiiZ1m062TNxDexT6EqeL9uKPoy_jVpX6yMzt2R9mV9PByPstI-t6qBnk7FcVc01WrA4aa6mei4do30KNY8O9R6ijZo_Rg1YRyyco3WQhXmchLlK8YiFesRBvsBC_BQ4eGQZiYCCuGYjBgmbgU3R5enJxfEbs7h1EeND9kkRw6aYB5dCDgCz0lFC-x4LUDcMIVLlDBUjj1JXK0xukCe6AM5FB4jtSSKFA2D5D3VkxU88RFoyGKbRk4TDww0REVLqgqTxXcTl0Q9ZDzuo_nAhb2l7vsDKd3IpdD72rm_wwdV3-dvPhCpiJff0XEz1S9x3KPL-HjjbAqk1umTq4y3NfoPvNC3OIuuV8qV6CBi75K0u5P3hopfc
linkProvider EBSCOhost
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=High-Performance+Implementation+of+Wideband+Coherent+Signal-Subspace+%28CSS%29-Based+DOA+Algorithm+on+FPGA&rft.jtitle=Journal+of+circuits%2C+systems%2C+and+computers&rft.au=Jarrah%2C+Amin&rft.au=Almomany%2C+Abedalmuhdi&rft.au=Alsobeh%2C+Anas+M.+R.&rft.au=Alqudah%2C+Eman&rft.date=2021-09-15&rft.issn=0218-1266&rft.eissn=1793-6454&rft.volume=30&rft.issue=11&rft.spage=2150196&rft_id=info:doi/10.1142%2FS0218126621501966&rft.externalDBID=n%2Fa&rft.externalDocID=10_1142_S0218126621501966
thumbnail_l http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0218-1266&client=summon
thumbnail_m http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0218-1266&client=summon
thumbnail_s http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0218-1266&client=summon