Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs

Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate （HK/MG） process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin str...

Full description

Saved in:
Bibliographic Details
Published inJournal of semiconductors Vol. 36; no. 4; pp. 66 - 69
Main Author 许淼 殷华湘 朱慧珑 马小龙 徐唯佳 张永奎 赵治国 罗军 杨红 李春龙 孟令款 洪培真 项金娟 高建峰 徐强 熊文娟 王大海 李俊峰 赵超 陈大鹏 杨士宁 叶甜春
Format Journal Article
LanguageEnglish
Published 01.04.2015
Subjects
Annealing
Channels
Devices
Doping
Drains
FinFET
Implantation
Magnesium
Semiconductors
参数优化
器件
散装
纳米
节点
设备参数
退火设备
Online AccessGet full text
ISSN1674-4926
DOI10.1088/1674-4926/36/4/044007

Cover

More Information
Summary:Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate （HK/MG） process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin structure. The punch through stop layer （PTSL） and source drain extension （SDE） doping profiles are carefully optimized. The device without SDE annealing shows a larger drive current than that with SDE annealing due to better Si crystal regrowth in the amorphous Fin structure after source/drain implantation. The band-edged MG has a better short channel effect immunity, but the lower effective work function （EWF） MG shows a larger driveability. A tradeoff choice for different EWF MGs should be carefully designed for the device＇s scaling.
Bibliography:bulk FinFET; effective work function （EWF）; extension thermal budget; metal gate
11-5781/TN
Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate （HK/MG） process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin structure. The punch through stop layer （PTSL） and source drain extension （SDE） doping profiles are carefully optimized. The device without SDE annealing shows a larger drive current than that with SDE annealing due to better Si crystal regrowth in the amorphous Fin structure after source/drain implantation. The band-edged MG has a better short channel effect immunity, but the lower effective work function （EWF） MG shows a larger driveability. A tradeoff choice for different EWF MGs should be carefully designed for the device＇s scaling.
ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
ISSN:1674-4926
DOI:10.1088/1674-4926/36/4/044007