A vertically integrated capacitorless memory cell

A two-port capacitorless PNPN device with high density,high speed and low power memory fabricated using standard CMOS technology is presented.Experiments and calibrated simulations were conducted which prove that this new memory cell has a high operation speed(ns level),large read current margin(rea...

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Bibliographic Details
Published inJournal of semiconductors Vol. 34; no. 8; pp. 65 - 69
Main Author 童小东 吴昊 赵利川 王明 钟汇才
Format Journal Article
LanguageEnglish
Published 01.08.2013
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ISSN1674-4926
DOI10.1088/1674-4926/34/8/084005

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Summary:A two-port capacitorless PNPN device with high density,high speed and low power memory fabricated using standard CMOS technology is presented.Experiments and calibrated simulations were conducted which prove that this new memory cell has a high operation speed(ns level),large read current margin(read current ratio of 10~4×),low process variation,good thermal reliability and available retention time(190 ms).Furthermore,the new memory cell is free of the cyclic endurance/reliability problems induced by hot-carrier injection due to the gateless structure.
Bibliography:A two-port capacitorless PNPN device with high density,high speed and low power memory fabricated using standard CMOS technology is presented.Experiments and calibrated simulations were conducted which prove that this new memory cell has a high operation speed(ns level),large read current margin(read current ratio of 10~4×),low process variation,good thermal reliability and available retention time(190 ms).Furthermore,the new memory cell is free of the cyclic endurance/reliability problems induced by hot-carrier injection due to the gateless structure.
Tong Xiaodong, Wu Hao Zhao Lichuan Wang Ming, and Zhong Huicai Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
PNPN diode two-port cross-point
11-5781/TN
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ISSN:1674-4926
DOI:10.1088/1674-4926/34/8/084005