A vertically integrated capacitorless memory cell - 童小东 吴昊 赵利川 王明 钟汇才 (Journal of semiconductors, 2013)
A two-port capacitorless PNPN device with high density,high speed and low power memory fabricated using standard CMOS technology is presented.Experiments and calibrated simulations were conducted which prove that this new memory cell has a high operation speed（ns level）,large read current margin（read current ratio of 10~4×）,low process variation,good thermal reliability and available retention time（190 ms）.Furthermore,the new memory cell is free of the cyclic endurance/reliability problems induced by hot-carrier injection due to the gateless structure.