A composite SystemC-UVM abstract optimal path selection verification architecture for complex designs - Sharma, Gaurav; Bhargava, Lava; Kumar, V. (Microelectronics and reliability, 2022)
Universal Verification Methodology (UVM) architectures are highly trained for stimulus generation and verification of System-on-chip (SoC). The cross-functional and cross-platform interactive verification is the limitation of a sole UVM architecture. Sole UVM objects are not efficient to satisfy cross-functional compatibility requirements. A system C verification libraries have a mechanism of introspection. The data introspection is not capable of wide cross-platform use without reusable portable accurate TLM. So a UVM module requires a SystemC block to aim for the cross-functional working of verification. The work shows a composite UVM-SystemC methodology to rationally adhere to optimal test path selection among all test paths. The work presents SC-UVM (SystemC-UVM) architecture for cross-platform working facilitation. The learning methodology works to improvise coverage parameters with the optimization of coverage bins. The methodology earns a significant contribution for early verification by reducing the internal data processing and simulation time. The SystemC-UVM method outperforms the conventional SystemVerilog and Sole UVM verification techniques. The work declares the improvement of 5.26% in simulation time with 5.11% lesser data processing for database creation in front of the sole UVM verification architecture. •The testbench uses multi-tasking using the composite platform to ease the verification process for cross platform working.•Implementation of smart learning skill-based algorithm for optimal path selection to allow only one main scenario.•The composite SystemC-UVM testbench is for execution across IP level, block-level, and physical fabrication level.