Impedance matching for the reduction of signal reflection in high speed multilevel three-dimensional integrated chips

• Published in: Journal of semiconductors Vol. 35; no. 1; pp. 121 - 128
• Main Author: 刘晓贤 朱樟明 杨银堂 王凤娟 丁瑞雪
• Format: Journal Article
• Language: English
• Published: 2014
• Subjects: Capacitance; High speed; Interconnections; Multilevel; Reduction; Semiconductors; Signal reflection; SV通道; Three dimensional; 三维集成电路; 互连结构; 信号反射; 多级; 调谐频率; 阻抗匹配; 集成芯片
• ISSN: 1674-4926
• DOI: 10.1088/1674-4926/35/1/015008

In high speed three-dimensional integrated circuits （3D ICs）, through silicon via （TSV） insertion causes impedance discontinuities along the interconnect-TSV channel that results in signal reflection. As demonstrated for a two-plane interconnect structure connected by a TSV, we incorporate an appropriate capacitance at the junction to mitigate the signal reflection with gigascale frequencies. Based on 65 nm technology and S-parameter analysis, the decrease of signal reflection can be 189% at the tuned frequency of 5 GHz. Extending this method to the five-plane interconnect structure further, the reduction of signal reflection can achieve 400%. So we could broaden this method to any multilevel 3D interconnect structures. This method can also be applied to a circuit with tunable operating frequencies by digitally connecting the corresponding matching capacitance into the circuit through switches. There are remarkable improvements of the quality of the transmitting signals.