APA (7th ed.) Citation

P, R., & H, M. (2021). Design and implementation of power and area optimized AES architecture on FPGA for IoT application. Circuit world, 47(2), 153-163. https://doi.org/10.1108/CW-04-2019-0039

Chicago Style (17th ed.) Citation

P, Rajasekar, and Mangalam H. "Design and Implementation of Power and Area Optimized AES Architecture on FPGA for IoT Application." Circuit World 47, no. 2 (2021): 153-163. https://doi.org/10.1108/CW-04-2019-0039.

MLA (9th ed.) Citation

P, Rajasekar, and Mangalam H. "Design and Implementation of Power and Area Optimized AES Architecture on FPGA for IoT Application." Circuit World, vol. 47, no. 2, 2021, pp. 153-163, https://doi.org/10.1108/CW-04-2019-0039.