A 50-neuron CMOS analog chip with on-chip digital learning: design, development, and experiments

• Published in: Computers & electrical engineering Vol. 25; no. 5; pp. 357 - 378
• Main Authors: Salam, Fathi, Wang, Yiwen, Oh, Hwa-Joon
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01.09.1999
• Subjects: Analog chip; Continuous-time learning algorithm; Dendro-dendritic Artificial Neural Network (DANN); Digital learning algorithm; Hardware interface circuitry; Synapse; Hardware interface circuitry; Dendro-dendritic Artificial Neural Network (DANN); Analog chip; Synapse; Digital learning algorithm; Continuous-time learning algorithm
• ISSN: 0045-7906; 1879-0755
• DOI: 10.1016/S0045-7906(99)00017-8

The model, implementation, and experimental application of a Dendro-dendritic Artificial Neural Network (DANN) with learning are presented. The DANN model lends itself to a direct all-MOS implementation. A learning algorithm is developed, then abstracted to a simple digital learning scheme. A 50-neuron analog chip with on-chip digital learning scheme is fabricated in 6800×4600 μm die size with 63,025 transistors and 1225 programmable synaptic weights in a standard 2 μ CMOS technology. Each synaptic weight is realized by a single (nonlinear) MOS transistor controlled via its gate-voltage. Two user-chosen analog gate-voltages are available to all synapses as two binary levels. The on-chip digital learning circuitry determines which binary level based on the desired patterns to be stored. Moreover, a synapse’s level can be assigned by the user or can be downloaded from an external source. Finally, we demonstrate the function of the chip, which is interfaced to a PC and augmented with graphical software, in three different experimental categories: (i) pattern recognition, (ii) edge detection, and (iii) as a locally connected network. The scalable architectural design and these three experimental categories show the chip’s versatile capabilities as a potential co-processor.