A 50-neuron CMOS analog chip with on-chip digital learning: design, development, and experiments - Salam, Fathi; Wang, Yiwen; Oh, Hwa-Joon (Computers & electrical engineering, 1999)
The model, implementation, and experimental application of a Dendro-dendritic Artificial Neural Network (DANN) with learning are presented. The DANN model lends itself to a direct all-MOS implementation. A learning algorithm is developed, then abstracted to a simple digital learning scheme. A 50-neuron analog chip with on-chip digital learning scheme is fabricated in 6800×4600 μm die size with 63,025 transistors and 1225 programmable synaptic weights in a standard 2 μ CMOS technology. Each synaptic weight is realized by a single (nonlinear) MOS transistor controlled via its gate-voltage. Two user-chosen analog gate-voltages are available to all synapses as two binary levels. The on-chip digital learning circuitry determines which binary level based on the desired patterns to be stored. Moreover, a synapse’s level can be assigned by the user or can be downloaded from an external source. Finally, we demonstrate the function of the chip, which is interfaced to a PC and augmented with graphical software, in three different experimental categories: (i) pattern recognition, (ii) edge detection, and (iii) as a locally connected network. The scalable architectural design and these three experimental categories show the chip’s versatile capabilities as a potential co-processor.