EPOC: A 28-nm 5.3 pJ/SOP Event-Driven Parallel Neuromorphic Hardware With Neuromodulation-Based Online Learning

Bio-inspired neuromorphic hardware with learning ability is highly promising to achieve human-like intelligence, particularly in terms of high energy efficiency and strong environmental adaptability. Though many customized prototypes have demonstrated learning ability, learning on neuromorphic hardw...

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Published inIEEE transactions on biomedical circuits and systems Vol. 19; no. 3; pp. 629 - 644
Main Authors Chen, Faquan, Tian, Qingyang, Xie, Lisheng, Zhou, Yifan, Wu, Ziren, Wu, Liangshun, Ying, Rendong, Wen, Fei, Liu, Peilin
Format Journal Article
LanguageEnglish
Published United States IEEE 01.06.2025
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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ISSN1932-4545
1940-9990
1940-9990
DOI10.1109/TBCAS.2024.3470520

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Summary:Bio-inspired neuromorphic hardware with learning ability is highly promising to achieve human-like intelligence, particularly in terms of high energy efficiency and strong environmental adaptability. Though many customized prototypes have demonstrated learning ability, learning on neuromorphic hardware still lacks a bio-plausible and unified learning framework, and inherent spike-based sparsity and parallelism have not been fully exploited, which fundamentally limits their computational efficiency and scale. Therefore, we develop a unified, event-driven, and massively parallel multi-core neuromorphic online learning processor, namely EPOC. We present a neuromodulation-based neuromorphic online learning framework to unify various learning algorithms, and EPOC supports high-accuracy local/global supervised Spike Neural Network (SNN) learning with a low-memory-demand streaming single-sample learning strategy through different neuromodulator formulations. EPOC leverages a novel event-driven computation method that fully exploits spike-based sparsity throughout the forward-backward learning phases, and parallel multi-channel and multi-core computing architecture, bringing 9.9<inline-formula><tex-math notation="LaTeX">\times</tex-math></inline-formula> time efficiency improvement compared with the baseline architecture. We synthesize EPOC in a 28-nm CMOS process and perform extensive benchmarking. EPOC achieves state-of-the-art learning accuracy of 99.2%, 98.2%, and 94.3% on the MNIST, NMNIST, and DVS-Gesture benchmarks, respectively. Local-learning EPOC achieves 2.9<inline-formula><tex-math notation="LaTeX">\times</tex-math></inline-formula> time efficiency improvement compared with the global learning counterpart. EPOC operates at a typical clock frequency of 100 MHz, providing a peak 328 GOPS/51 GSOPS throughput and a 5.3 pJ/SOP energy efficiency.
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ISSN:1932-4545
1940-9990
1940-9990
DOI:10.1109/TBCAS.2024.3470520