Advanced Implementation of DNN Translator using ResNet9 for Edge Devices
Resource limitations remain challenging in designing and implementing Deep Neural Networks (DNNs) on edge devices. The high complexity of DNN architectures and the development of these models using hardware languages require high-level verification to ensure they run on specific edge devices such as...
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| Published in | International Journal of Networking and Computing Vol. 14; no. 2; pp. 145 - 156 |
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| Main Authors | , , , , |
| Format | Journal Article |
| Language | English |
| Published |
IJNC Editorial Committee
2024
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| Subjects | |
| Online Access | Get full text |
| ISSN | 2185-2839 2185-2847 2185-2847 |
| DOI | 10.15803/ijnc.14.2_145 |
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| Abstract | Resource limitations remain challenging in designing and implementing Deep Neural Networks (DNNs) on edge devices. The high complexity of DNN architectures and the development of these models using hardware languages require high-level verification to ensure they run on specific edge devices such as FPGA (Field Programmable Gate Array). To address these issues, the DNN translator was developed and performed well in the basic models such as MLP (Multi-layer Perceptron) and LeNet5. The DNN translator generates the DNN models and their parameters for performing the High-Level Synthesis or HLS technology in C++. In this study, we applied ResNet as a DNN model with more complex architecture from the CNNs (Convolutional Neural Networks) family. As a result, the generated C++ files for the ResNet9 and its weights successfully underwent synthesis and implementation on FPGA (Arty A7-100) using Vitis HLS. |
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| AbstractList | Resource limitations remain challenging in designing and implementing Deep Neural Networks (DNNs) on edge devices. The high complexity of DNN architectures and the development of these models using hardware languages require high-level verification to ensure they run on specific edge devices such as FPGA (Field Programmable Gate Array). To address these issues, the DNN translator was developed and performed well in the basic models such as MLP (Multi-layer Perceptron) and LeNet5. The DNN translator generates the DNN models and their parameters for performing the High-Level Synthesis or HLS technology in C++. In this study, we applied ResNet as a DNN model with more complex architecture from the CNNs (Convolutional Neural Networks) family. As a result, the generated C++ files for the ResNet9 and its weights successfully underwent synthesis and implementation on FPGA (Arty A7-100) using Vitis HLS. |
| Author | Ito, Masayoshi Morishita, Yuki Diana, Mery Kiyama, Masato Amagasaki, Motoki |
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| Cites_doi | 10.1145/3495531 10.1109/MSP.2012.2211477 10.1016/j.procs.2020.07.006 10.1145/3204919.3204929 10.3390/electronics9122200 10.1109/DSN-W50199.2020.00014 10.1109/ICCAD.2017.8203809 10.1109/TCAD.2017.2785257 10.1145/3358182 10.1109/TCAD.2015.2513673 10.1145/2789116.2789145 10.1109/CANDARW60564.2023.00017 10.1145/2539036.2539048 10.1145/3486674 |
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| References_xml | – reference: [4] Li Deng. The mnist database of handwritten digit images for machine learning research. IEEE Signal Processing Magazine, 29(6):141–142, 2012. – reference: [11] A. Mahmoud, N. Aggarwal, A. Nobbe, J. R. S. Vicarte, S. V. Adve, C. W. Fletcher, I. Frosio, and S. K. S. Hari. Pytorchfi: A runtime perturbation tool for dnns. In Proceeding of 2020 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), pages 25–31, 2020. – reference: [15] Adam Paszke, Sam Gross, Francisco Massa, Adam Lerer, James Bradbury, Gregory Chanan, Trevor Killeen, Zeming Lin, Natalia Gimelshein, Luca Antiga, Alban Desmaison, Andreas Kopf, Edward Yang, Zachary DeVito, Martin Raison, Alykhan Tejani, Sasank Chilamkurthy, Benoit Steiner, Lu Fang, Junjie Bai, and Soumith Chintala. Pytorch: An imperative style, high-performance deep learning library. https://pytorch.org, 2021. – reference: [20] Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, and Bingsheng He. Comba: A comprehensive model-based analysis framework for high level synthesis of real applications. In Proceeding of 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 430–437, 2017. – reference: [14] Katharina Ostaszewski, Philip Heinisch, and Hendrik Ranocha. Advantages and pitfalls of opencl in computational physics. In Proceedings of the International Workshop on OpenCL, IWOCL '18, New York, NY, USA, 2018. – reference: [3] Olivier Debauche, Saïd Mahmoudi, Sidi Ahmed Mahmoudi, Pierre Manneback, and Frédéric Lebeau. A new edge architecture for ai-iot services deployment. Procedia Computer Science, 175:10–19, 2020. – reference: [16] Zi Wang and Benjamin Carrion Schafer. Learning from the past: Efficient high-level synthesis design space exploration for fpgas. ACM Trans. Des. Autom. Electron. Syst., 27(4), 2022. – reference: [19] Chen Zhang, Guangyu Sun, Zhenman Fang, Peipei Zhou, Peichen Pan, and Jason Cong. Caffeine: Toward uniformed representation and acceleration for deep convolutional neural networks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 38(11):2072–2085, 2019. – reference: [1] Donald G. Bailey. The advantages and limitations of high level synthesis for fpga based image processing. In Proceedings of the 9th International Conference on Distributed Smart Cameras, ICDSC '15, page 134–139, 2015. – reference: [17] Xilinx, Inc. Xilinx vitis high-level synthesis (hls) documentation, 2022. accessed May 14. – reference: [18] Dianlei Xu, Tong Li, Yong Li, Xiang Su, Sasu Tarkoma, Tao Jiang, Jon Crowcroft, and Pan Hui. Edge Intelligence: Architectures, Challenges, and Applications, June 2020. arXiv:2003.12172 [cs]. – reference: [8] Andreas Kloeckner and Contributors. cgen -code generation library. https://github.com/inducer/cgen, 2020. accessed May 12. – reference: [13] Razvan Nane, Vlad-Mihai Sima, Christian Pilato, Jongsok Choi, Blair Fort, Andrew Canis, Yu Ting Chen, Hsuan Hsiao, Stephen Brown, Fabrizio Ferrandi, Jason Anderson, and Koen Bertels. A survey and evaluation of fpga high-level synthesis tools. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35(10):1591–1604, 2016. – reference: [5] Diana, Mery, Kiyama, Masato, Amagasaki, Motoki, Ito, Masayoshi, and Morishita, Yuki. Deep neural network translator for edge site implementation. In Proceeding of 2023 Eleventh International Symposium on Computing and Networking Workshops (CANDARW), page 52, Matsue, Japan, nov 2023. – reference: [2] Yosi Ben-Asher and Nadav Rotem. The benefits of using variable-length pipelined operations in high-level synthesis. ACM Trans. Embed. Comput. Syst., 13(3), dec 2013. – reference: [9] A. Krizhevsky and G. Hinton. Learning multiple layers of features from tiny images. Master's thesis, Department of Computer Science, University of Toronto, 2009. – reference: [10] Marcos T. Leipnitz and Gabriel L. Nazar. High-level synthesis of approximate designs under real-time constraints. ACM Trans. Embed. Comput. Syst., 18(5s), oct 2019. – reference: [7] Kaiming He, Xiangyu Zhang, Shaoqing Ren, and Jian Sun. Deep residual learning for image recognition, 2015. – reference: [12] Javier Mendez, Kay Bierzynski, M. P. Cuéllar, and Diego P. Morales. Edge intelligence: Concepts, architectures, applications, and future directions. ACM Trans. Embed. Comput. Syst., 21(5), oct 2022. – reference: [6] Alireza Ghaffari and Yvon Savaria. Cnn2gate: An implementation of convolutional neural networks inference on fpgas with automated design space exploration. Electronics, 9(12), 2020. – ident: 17 – ident: 18 – ident: 16 doi: 10.1145/3495531 – ident: 4 doi: 10.1109/MSP.2012.2211477 – ident: 3 doi: 10.1016/j.procs.2020.07.006 – ident: 14 doi: 10.1145/3204919.3204929 – ident: 6 doi: 10.3390/electronics9122200 – ident: 11 doi: 10.1109/DSN-W50199.2020.00014 – ident: 20 doi: 10.1109/ICCAD.2017.8203809 – ident: 15 – ident: 19 doi: 10.1109/TCAD.2017.2785257 – ident: 10 doi: 10.1145/3358182 – ident: 13 doi: 10.1109/TCAD.2015.2513673 – ident: 1 doi: 10.1145/2789116.2789145 – ident: 5 doi: 10.1109/CANDARW60564.2023.00017 – ident: 9 – ident: 2 doi: 10.1145/2539036.2539048 – ident: 7 – ident: 8 – ident: 12 doi: 10.1145/3486674 |
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| SubjectTerms | Deep Neural Network Translator Edge Site High-Level Synthesis ResNet9 |
| Title | Advanced Implementation of DNN Translator using ResNet9 for Edge Devices |
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