A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing

• Published in: IEEE journal of solid-state circuits Vol. 51; no. 1; pp. 303 - 309
• Main Authors: Yamaoka, Masanao, Yoshimura, Chihiro, Hayashi, Masato, Okuyama, Takuya, Aoki, Hidetaka, Mizuno, Hiroyuki
• Format: Journal Article
• Language: English
• Published: IEEE 01.01.2016
• Subjects: Annealing; Chips; Circuits; CMOS; CMOS annealing; CMOS integrated circuits; Combinatorial analysis; combinatorial optimization problem; Computation; Computational modeling; Computer architecture; Integrated circuit modeling; Ising computing; Ising model; natural computing; Optimization; Semiconductor device modeling; SRAM; variation; Ising computing; combinatorial optimization problem; Ising model; natural computing; CMOS annealing; SRAM; variation
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2015.2498601

In the near future, the ability to solve combinatorial optimization problems will be a key technique to enable the IoT era. A new computing architecture called Ising computing and implemented using CMOS circuits is proposed. This computing maps the problems to an Ising model, a model to express the behavior of magnetic spins, and solves combinatorial optimization problems efficiently exploiting its intrinsic convergence properties. In the computing, "CMOS annealing" is used to find a better solution for the problems. A 20k-spin prototype Ising chip is fabricated in 65 nm process. The Ising chip achieves 100 MHz operation and its capability of solving combinatorial optimization problems using an Ising model is confirmed. The power efficiency of the chip can be estimated to be 1800 times higher than that of a general purpose CPU when running an approximation algorithm.