Speed/Area-Efficient ECC Processor Implementation Over GF(2 ^m) on FPGA via Novel Algorithm-Architecture Co-Design - Zeghid, Medien; Ahmed, Hassan Yousif; Chehri, Abdellah; Sghaier, Anissa (IEEE transactions on very large scale integration (VLSI) systems, 2023)
With the rapid evolution of security technology, small field-size elliptic curve-based point multiplication (PM) has gradually become obsolete, leading to the implementation of PM with large field sizes. From this perspective, in this article, through a novel algorithm-architecture co-design strategy, we propose an efficient implementation of the PM on the elliptic curve over GF(2 ^m) (particularly targeting large field sizes). To achieve an area-time-efficient elliptic curve cryptography (ECC) processor implementation on the field-programmable gate array (FPGA) platform, we have proposed a bottom-up approach based on three coherent interdependent layers of efforts. First, we proposed an efficient digit-serial versatile multiplier (DSVM) based on polynomial representation. The system is built using the four-way overlap-free Karatsuba algorithm (OFKA) and a modified radix-n interleaved multiplication (mRnIM) technique (for area and time complexities reduction). Of course, the efficiency of the proposed multiplier is demonstrated by the complexity analysis and comparison with the existing reported designs. Second, we have adopted the López-Dahab (LD) Montgomery PM algorithm to avoid data dependency and enhance signal control in the ECC design. Meanwhile, a series of resource optimization techniques have also been adopted for the proposed ECC processor to optimize the overall design efficiency further. Third, the proposed ECC PM architecture is then implemented on the FPGA platform, showing that the proposed ECC crypto-processor obtains the least area-delay product (ADP) among all the existing structures for the large field sizes.