Design of Approximate Booth Squarer for Error-Tolerant Computing - Manikantta Reddy, K.; Vasantha, M. H.; Nithin Kumar, Y. B.; Dwivedi, Devesh (IEEE transactions on very large scale integration (VLSI) systems, 2020)
To explore the benefits of approximate computing, this article proposes an approximate partial product generator for squarer (APPGS). Using APPGS, three designs of approximate radix-4 Booth squarers (ABS1, ABS2, and ABS3) are proposed. APPGS produces approximate partial products in r number of least significant columns of the partial product matrix. ABS2 and ABS3 utilize approximate adders and compressors with a novel input signal rearrangement method for the accumulation of approximate partial products. Moreover, the ABS3 features an error recovery module at k number of most significant columns of the approximate partial products. The proposed squarers with different values of r and k are simulated using 45-nm CMOS technology. The results indicate that the proposed squarers achieve optimized performance for both hardware and accuracy metrics. Compared to the exact Booth squarer, the 16-bit ABS1 with r=16 achieves a reduction of 13.6%, 22.2%, and 13.7% in power, delay, and area, respectively, with a normalized mean error distance (NMED) of 4.6× 10^{-6} . The ABS2 has power, delay, and area savings of 25.8%, 33.8%, and 19.8%, respectively, with an NMED of 7.2× 10^{-6} . The ABS3 with k=6 has 18.5% reduction in power, 29.4% reduction in delay, and 16.9% reduction in area with an NMED of 0.56× 10^{-6} . The performance of the proposed squarers is evaluated with a telecommunication application, where the ABS3 with k=6 produces an output signal with a signal-to-noise ratio of 32.45 dB.