Design of an S-ECIES Cryptoprocessor Using Gaussian Normal Bases Over GF(2m) - Realpe-Munoz, Paulo; Velasco-Medina, Jaime; Adolfo-David, Guillermo (IEEE transactions on very large scale integration (VLSI) systems, 2021)
In this article, we present the design of a high-performance simplified elliptic curve integrated encryption scheme (S-ECIES) cryptoprocessor. The cryptoprocessor was designed using a Montgomery ladder scalar multiplier, which was implemented with three finite field multipliers to improve the computational time of the scalar multiplication {kP} , and using random curves and Gaussian normal bases over GF(2 163 ) and GF(2 233 ). Also, considering the National Institute of Standards and Technology (NIST) recommendations, a true random number generator is implemented to generate a secret key k , which is used during the encryption process. The S-ECIES cryptoprocessor was synthesized on field-programmable gate array (FPGA) Stratix IV EP4SGX230KF40C2, simulated in ModelSim, and verified in hardware using the DE4 board and SignalTap tool. According to the synthesis results, the scalar multiplication operation is performed in 5.31 and 8.77~μ \text{s} for GF(2 163 ) and GF(2 233 ), respectively. Also, the encryption process is performed in 20.70 and 30.90~μ \text{s} for GF(2 163 ) and GF(2 233 ), respectively, and the decryption process is calculated in 8.10 and 11.9~μ \text{s} for GF(2 163 ) and GF(2 233 ), respectively. The consumption power for the S-ECIES is 921 and 935 mW for GF(2 163 ) and GF(2 233 ), respectively.