A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 28; no. 12; pp. 2708 - 2720
• Main Authors: Joo, Hye-Yoon, Lee, Jinhyung, Ju, Haram, Ko, Han-Gon, Yoon, Jung Min, Kang, Byungjun, Jeong, Deog-Kyoon
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Bit error rate; Bit error rate (BER); clock and data recovery (CDR); Clock recovery; CMOS; Data recovery; decision feedback equalizer (DFE); Decision feedback equalizers; Eye movements; Feedback communications; Hardware; high-speed links; Intersymbol interference; Least mean squares methods; precursor intersymbol interference (ISI); Samplers; Sampling; sampling point control; sign–sign least-mean-square (SS-LMS) algorithm; timing adaptation; Tracking; Very large scale integration
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2020.3029079

In this article, a maximum-eye-tracking clock and data recovery (MET-CDR) circuits for minimum bit error rate (BER) are presented. The proposed CDR does not require a BER counter or an eye-opening monitor with any iterative procedure to find the optimal sampling phase. The biased data level obtained from the weighted sum of error sampler outputs provides the actual eye height (EH) information in the presence of precursor intersymbol interference (ISI). Two samplers operating on two slightly different timings detect the current EH and the polarity of the eye slope so that the CDR can track the maximum EH where the slope becomes zero. Measured results show that the sampling phase of the maximum EH and that of the minimum BER match well. A prototype receiver fabricated in 28-nm CMOS process operates at 26 Gb/s with an eye-opening of 0.25 unit interval (UI) and consumes 87 mW while equalizing 23.5 dB of loss at 13 GHz.