Impact of Radix-10 Redundant Digit Set [−6, 9] on Basic Decimal Arithmetic Operations

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 30; no. 1; pp. 51 - 59
• Main Authors: Jaberipur, Ghassem, Ghazanfari, Farzad
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adders; Adding circuits; Arithmetic; Carry-free addition (CFA); Costs; decimal computer arithmetic; Delays; Encoding; Logic gates; Redundancy; redundant number system (RDNS); Representations; Very large scale integration; very large-scale integration (VLSI) design
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2021.3120065

Redundant-digit decimal computer arithmetic, with the principal property of carry-free addition, has been the subject of several studies, as the relevant literature contains a wide variety of decimal digit sets and their binary representations. For example, symmetric decimal signed digit sets <inline-formula> <tex-math notation="LaTeX">[-\alpha, \alpha] </tex-math></inline-formula>, for <inline-formula> <tex-math notation="LaTeX">\alpha \in \{5,6,7,8,9 \} </tex-math></inline-formula>, and the asymmetric ones, such as [−8, 9], [−9, 7], and [0, 15], have been the basis of variant hardware architectures for decimal arithmetic operations. However, digit sets with the minimal 4-bit representations show better figures of merit. In this work, we present a new decimal digit set [−6, 9], called diminished-6 overloaded decimal digit set (DODDS). Its special 4-bit representation contains two posibits (weighted <inline-formula> <tex-math notation="LaTeX">2^{3} </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">2^{0} </tex-math></inline-formula>) and two negabits (weighted <inline-formula> <tex-math notation="LaTeX">2^{2} </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">2^{1} </tex-math></inline-formula>). Design and implementation of the corresponding carry-free decimal adders and subtractors are thoroughly discussed. Furthermore, to cover the requirements of all possible DODDS applications in decimal multipliers, dividers, and square rooters, we provide adder/subtractor designs for a variety of input combinations of DODDS and binary coded decimal (BCD) operands, all with DODDS output (e.g., DODDS + BCD = DODDS, which is useful in BCD partial product reduction). Analytical and synthesis-based evaluations and comparisons with similar previous works show the notable merits of DODDS over the other redundant decimal digit sets.