An Algorithm-Hardware Co-Optimized Framework for Accelerating N:M Sparse Transformers

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 30; no. 11; pp. 1573 - 1586
• Main Authors: Fang, Chao, Zhou, Aojun, Wang, Zhongfeng
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Algorithm–hardware codesign; Computational modeling; Constraint modelling; Engines; Field programmable gate arrays; Graphics processing units; Hardware; hardware accelerator; Machine learning; model compression; Network latency; Optimization; pruning; Sparse matrices; Sparsity; Transformer; Transformers
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2022.3197282

The Transformer has been an indispensable staple in deep learning. However, for real-life applications, it is very challenging to deploy efficient Transformers due to the immense parameters and operations of models. To relieve this burden, exploiting sparsity is an effective approach to accelerate Transformers. Newly emerging Ampere graphics processing units (GPUs) leverage a 2:4 sparsity pattern to achieve model acceleration, while it can hardly meet the diverse algorithm and hardware constraints when deploying models. By contrast, we propose an algorithm-hardware co-optimized framework to flexibly and efficiently accelerate Transformers by utilizing general N:M sparsity patterns. First, from an algorithm perspective, we propose a sparsity inheritance mechanism along with inherited dynamic pruning (IDP) to obtain a series of N:M sparse candidate Transformers rapidly. A model compression scheme is further proposed to significantly reduce the storage requirement for deployment. Second, from a hardware perspective, we present a flexible and efficient hardware architecture, namely, STA, to achieve significant speedup when deploying N:M sparse Transformers. STA features not only a computing engine unifying both sparse-dense and dense-dense matrix multiplications with high computational efficiency but also a scalable softmax module eliminating the latency from intermediate off-chip data communication. Experimental results show that, compared to other methods, N:M sparse Transformers, generated using IDP, achieves an average of 6.7% improvement on accuracy with high training efficiency. Moreover, STA can achieve <inline-formula> <tex-math notation="LaTeX">14.47\times </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">11.33\times </tex-math></inline-formula> speedups compared to Intel i9-9900X and NVIDIA RTX 2080 Ti, respectively, and perform <inline-formula> <tex-math notation="LaTeX">2.00 \,\,\sim 19.47 \times </tex-math></inline-formula> faster inference than the state-of-the-art field-programmable gate array (FPGA)-based accelerators for Transformers.