Closed-Form Determination of the Impedance Locus Plot of Fault Current Limiters: A Rigorous Approach With Graphical Representation

• Published in: IEEE transactions on power delivery Vol. 33; no. 6; pp. 2710 - 2717
• Main Authors: Behzadirafi, Shayan, de Leon, Francisco
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuit faults; Circuits; Current distribution; Current limiters; Fault current limiters; Fault currents; Graphical representations; Impedance; Impedance matrix; Loci; Manufacturers; Mathematical analysis; Matrix methods; Power system reliability; power systems; root locus; short circuit calculation; Short circuit currents; superposition; Superposition (mathematics); Utilities
• ISSN: 0885-8977; 1937-4208
• DOI: 10.1109/TPWRD.2018.2839566

In this paper, a mathematically rigorous method is presented to calculate the impedance of FCLs based on a desirable change of short circuit currents. The method is found on the principle of superposition and can be easily incorporated into standard short circuit current calculations of power systems. The changes of the short circuit currents for each FCL installed are easily calculated without having to build a new impedance matrix for each new case. In addition, the method gives a clear graphical representation of the impact of the FCL on the power system taking advantage of the FCL impedance locus in the complex plane. The resultant plots provide valuable insight and information to utilities, system planners, and FCL manufacturers. FCL manufacturers can use these plots to identify the FCL impedance value and angle subject to the manufacturing and system constraints. The plots also allow utilities and system planners to compute the changes of fault current distribution caused by the FCL quickly and accurately. Results show that FCLs can increase short circuit currents in other branches. High-limiting FCLs may cause larger increase in short circuit currents of other branches and therefore a compromise may have to be made between fault current limitation and the maximum additional currents that are acceptable in other branches. Examples on a three-bus system and an eleven-bus system are presented for illustration and validation.