Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network - Chaurasiya, Rohit B.; Shrestha, Rahul (IEEE transactions on very large scale integration (VLSI) systems, 2022)
This article proposes implementation-friendly Gerschgorin radii and center ratio (GRCR)-based cooperative spectrum sensing (CSS) algorithm with reduced computational complexity that delivers adequate performance in uniform- and nonuniform-dynamical noise-and-received signal power scenarios. Subsequently, a new VLSI architecture of cooperative spectrum sensor (CSR) based on the proposed GRCR algorithm and additional architectural optimization has been suggested that consumes lower area and delivers shorter sensing time. Performance analysis of our implementation-friendly GRCR-based CSS algorithm has been carried out under the Rayleigh fading channel, and it delivers adequate area under the receiver-operating-characteristic (ROC) curve (AUC) = 0.9 at an average signal-to-noise ratio (SNR avg ) of −5 dB. Consecutively, an application-specific integrated circuit (ASIC) chip of the proposed CSR has been fabricated in the UMC 130-nm CMOS process. It occupies 0.27 mm 2 of the core area, and its maximum operating frequency is 88.8 MHz at 1.2 V of the supply voltage. At this clock frequency, our CSR delivers a sensing time of 5~μ \text{s} while processing the received signal samples from four secondary users in a cognitive-radio network. These ASIC-implementation results are compared with the reported works in the literature where our design has shown 45× and 12× better hardware efficiency and sensing time, respectively, compared to the state-of-the-art implementations.