Hardware-Efficient and High-Throughput LLRC Segregation Based Binary QC-LDPC Decoding Algorithm and Architecture - Verma, Anuj; Shrestha, Rahul (IEEE transactions on circuits and systems. II, Express briefs, 2021)
Keywords: Algorithms; Architecture; Codes; Computer architecture; Decoding; field-programmable gate-array (FPGA); frame error rate (FER); Hardware; Parallel processing; quasi-cyclic low-density-parity-check (QC-LDPC) codes; Routing; Signal to noise ratio; signal-to-noise ratio (SNR); Throughput; Wireless communication