Optimized Pulse Patterns with Bounded Semiconductor Losses

• Published in: IEEE transactions on power electronics Vol. 39; no. 3; pp. 1 - 11
• Main Authors: Geyer, Tobias, Karamanakos, Petros, Koukoula, Isavella
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Distortion; Harmonic analysis; Harmonic distortion; Harmonics; Optimization; Optimized pulse patterns; Pareto optimal solutions; semiconductor losses; Switches; Switching; Switching loss; three-level converters; Upper bounds; Voltage
• ISSN: 0885-8993; 1941-0107
• DOI: 10.1109/TPEL.2023.3337329

This paper proposes the computation of three-level optimized pulse patterns (OPPs) that achieve not only low harmonic load current distortions (load-friendly operation) but also low semiconductor losses (converter-friendly operation). To this end, the conduction and switching losses are modeled as a function of the OPP switching angles and the amplitude and phase of the converter current. By minimizing the current harmonics subject to an inequality constraint on the semiconductor losses, OPPs are derived that achieve minimal current distortions with a guaranteed upper bound on the semiconductor losses, thus ensuring the safe operation of the semiconductor switches within their thermal limits. Detailed numerical results for a mediumvoltage system consisting of a neutral-point-clamped converter and an inductive load verify the benefits of this approach.