RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 42; no. 3; pp. 712 - 725
• Main Authors: Ebrahimi, Zahra, Zaid, Muhammad, Wijtvliet, Mark, Kumar, Akash
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Application specific integrated circuits; Approximate computing; Approximation algorithms; Architecture; biosignal processing; Compressors; Computer architecture; Customization; divider; Dividers; Dividing (mathematics); energy efficiency; Field programmable gate arrays; field-programmable gate arrays (FPGAs); high throughput; Image processing; Kernels; Lookup tables; Mitchell’s algorithm; Moving object recognition; Multiplication; multiplier; Multipliers; pipeline; Pipeline processing; Table lookup; Throughput; Tracking; Unmanned aerial vehicles; unmanned aerial vehicles (UAVs)
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2022.3184928

The rapid updates in error-resilient applications along with their quest for high throughput has motivated designing fast approximate functional units for field-programmable gate arrays (FPGAs). Studies have proposed various imprecise functional techniques, albeit posed with three shortcomings: first, most existing inexact multipliers and dividers are specialized for application-specific integrated circuit (ASIC) platforms. Therefore, due to the architectural differences of underlying building blocks in FPGA and ASIC, ASIC-customized designs have not yielded comparable improvements when directly synthesized and ported to FPGAs. Second, state-of-the-art (SoA) approximate units are substituted, mostly in a single kernel of a multikernel application. Moreover, the end-to-end assessment is adopted on the quality of results (QoR), but not on the overall gained performance. Finally, the existing imprecise components are not designed to support a pipelined approach, which could boost the operating frequency/throughput of, e.g., division-included applications. In this article, we propose RAPID, the first pipelined approximate multiplier and divider architectures, customized for FPGAs. The proposed units efficiently utilize 6-input look-up tables (6-LUTs) and fast carry chains to implement Mitchell's approximate algorithms. Our novel error-refinement scheme not only has negligible overhead over the baseline Mitchell's approach but also boosts its accuracy to 99.4% for arbitrary size of multiplication and division. Experimental results obtained with Xilinx Vivado demonstrate the efficiency of the proposed pipelined and nonpipelined RAPID multipliers and dividers over accurate counterparts. In particular, the 4-stage pipelined architecture of a 32-bit RAPID multiplier (divider) enables <inline-formula> <tex-math notation="LaTeX">3.3\times </tex-math></inline-formula> (<inline-formula> <tex-math notation="LaTeX">5.1\times </tex-math></inline-formula>) higher throughput, <inline-formula> <tex-math notation="LaTeX">2.3\times </tex-math></inline-formula> (<inline-formula> <tex-math notation="LaTeX">6.8\times </tex-math></inline-formula>) higher throughput/Watt, and 52% (31%) savings of look-up tables (LUTs), over their 4-stage pipelined, accurate Intellectual Property (IP) counterparts. Moreover, the end-to-end evaluations of nonpipelined RAPID, deployed in three multikernel applications in the domains of biosignal processing, image processing, and moving object tracking for unmanned aerial vehicles (UAVs) indicate up to 35%, 33%, and 45% improvements in area, latency, and area-delay-product (ADP), respectively, over accurate kernels, with negligible loss in QoR. To springboard future research in reconfigurable and approximate computing communities, our implementations will be available and opensourced at https://cfaed.tu-dresden.de/pd-downloads .