A 65 nm Wireless Image SoC Supporting On-Chip DNN Optimization and Real-Time Computation-Communication Trade-Off via Actor-Critical Neuro-Controller

• Published in: IEEE journal of solid-state circuits Vol. 57; no. 8; pp. 2545 - 2559
• Main Authors: Cao, Ningyuan, Chatterjee, Baibhab, Liu, Jianbo, Cheng, Boyang, Gong, Minxiang, Chang, Muya, Sen, Shreyas, Raychowdhury, Arijit
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Artificial neural networks; Circuit design; Cloud computing; Communication; Computing time; Controllers; Costs; Decision making; Digital imaging; Digital to analog converters; Distance learning; Edge computing; Edge intelligence (EI); edge-cloud trade-off; Handheld computers; Image edge detection; Image processing; Internet of Things; Internet of Things (IoT); Machine learning; Microprocessors; Network latency; Neural networks; Optimization; Radio frequency; Real time; Reconfiguration; Smart sensors; System on chip; Tradeoffs; Transceivers; Wireless communication; Wireless sensor networks; wireless system-on-chip
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2022.3159473

The widespread proliferation of smart sensors has led to hardware that enable edge intelligence (EI) with extreme energy efficiencies. This decreases the volume of data that is transmitted to the cloud, thus reducing: 1) processing latency; 2) communication energy; and 3) network congestion. However, this comes with an added cost of computation at the edge node. The cost (energy/latency) of edge computation and the cost of communication to the cloud vary widely depending on operating conditions, which include: 1) information content in the data; 2) algorithm selection; 3) channel conditions (noise, path-loss, etc.); 4) network size, available bandwidth; and 5) resources at the cloud. This article presents a 65 nm wireless image processing SoC for real-time computation-communication trade-off on resource-constrained edge devices. The test-chip includes: 1) an all-digital, near-memory, reconfigurable, and programmable neural-network (NN)-based systolic image processor; 2) a digitally adaptive radio-frequency digital-to-analog converter (RF-DAC)-based transceiver; and 3) a mixed-signal, time-based, actor-critic (AC) neuro-controller with compute-in-memory (CIM) and in-place weight updates that provide online learning and adaptation for efficiently controlling the computation, communication blocks separately as well as jointly. The major contributions of the proposed SoC are threefold: 1) a wireless Internet of Things (IoT) SoC architecture enabling a generic computation-communication trade-off scheme; 2) a novel CIM circuit design enabling effective AC control and online learning (0.59 pJ/MAC, 0.4 pJ/update); 3) integration of programmable deep NN (DNN) accelerator (1.05 TOPS/W) and reconfigurable transceiver (184 pJ/b @ -15 dBm) supporting versatile cloud-edge collaborations; and 4) significant system-level energy efficiency improvement (5.7<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula>) with real-time on-chip smart control enabled by seamless chip integration and AI-enabled decision-making. Furthermore, this SoC serves as a system-level IoT prototype for next-generation context-aware EI.