A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 65; no. 7; pp. 2196 - 2209
• Main Authors: Khaleghi, Behnam, Asadi, Hossein
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.07.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuits; Computer architecture; Configurations; Delay; Emerging non-volatile memory; Field programmable gate arrays; Gate arrays; Phase change materials; Programming; programming circuitry; Random access memory; Reliability engineering; Resistance; resistive fluctuation; resistive random access memory; Static random access memory; Structural reliability; Table lookup; Variations
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2017.2778113

Despite the considerable effort has been put on the application of Non-Volatile Memories (NVMs) in Field-Programmable Gate Arrays FPGAs, previously suggested designs are not mature enough to substitute the state of-the-art SRAM-based counterparts mainly due to the inefficient building blocks and/or the overhead of programming structure which can impair their potential benefits. In this paper, we present a Resistive Random Access Memory RRAM-based FPGA architecture employing efficient Switch Box (SB) and Look-Up Table (LUT) designs with programming circuitry integrated in both SB and LUT designs that creates area and power efficient programmable components while precluding performance overhead to these blocks. In addition, we present an efficient scheme to load the configuration bitstream into the memory elements, which makes the configuration time comparable to that of SRAM-based FPGAs. Besides, we investigate the correct functionality and reliability of the programming structure subject to fluctuations in attributes of RRAM cells. Using Versatile Place and Route (VTR) tool with the obtained characteristics of the proposed blocks demonstrate that the average area and delay of the proposed FPGA architecture are 59.4% and 20.1% less than conventional SRAM-based FPGAs. Compared with a recent RRAM-based architecture, the proposed architecture improves the area and power by 49.7% and 33.8% while keeps the delay intact.