A CT 2-2 MASH ΔΣ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction - Fukazawa, Mitsuya; Oshima, Takashi; Fujiwara, Masaki; Tateyama, Katsuki; Ochi, Atsushi; Alsubaie, Raed; Matsui, Tetsuo (IEEE journal of solid-state circuits, 2021)
This article presents a continuous-time (CT) multistage noise-shaping (MASH) delta-sigma ( Δ Σ ) analog-to-digital converter (ADC) with enhanced tolerance to temperature and operating-frequency variations through on-chip multi-rate (MR) background calibration based on the least-mean-square (LMS) algorithm. The proposed digital calibration, which combines MR operation, post-conditioners, and pseudorandom-noise injection at the quantizer input, efficiently and accurately matches digital transfer functions to the corresponding analog ones for cancellation of quantization error. The first modulator in the proposed MASH ADC considers sufficient quantizer delay and reduces input-signal leakage into the second modulator to enable successful quantization-error transmission while minimizing distortion in the second stage, which cannot be tolerated in the case of calibrated digital noise-cancellation filter. A CT 2-2 MASH Δ Σ ADC prototype fabricated in 40-nm CMOS achieves the dynamic range (DR) of 79 dB and the signal-to-noise and distortion ratio (SNDR) of 78.5 dB over an 8-MHz bandwidth with 7.3-mW analog power and 16-mW digital power, reaching Schreier figure of merit (FoMs) of 168.9 dB, and demonstrates conversion-accuracy robustness within 1-dB SNDR fluctuation for temperature variations from −40° to 125° and within 2-dB SNDR degradation for frequency variations of 20% range.