ARBSA: Adaptive Range-Based Simulated Annealing for FPGA Placement

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 38; no. 12; pp. 2330 - 2342
• Main Authors: Yuan, Junqi, Chen, Jialing, Wang, Lingli, Zhou, Xuegong, Xia, Yinshui, Hu, Jianping
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adaptive algorithms; Benchmarks; Circuit design; Circuit topology; Computer simulation; Critical path; Digital signal processors; Field programmable gate array (FPGA); Field programmable gate arrays; Optimization; Placement; Random access memory; Reduction; Signal processing; Simulated annealing; simulated annealing (SA); Topology; Wire; Wire drawing
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2018.2878180

Placement has always been the most time-consuming part of the field programmable gate array (FPGA) compilation flow. Conventional simulated annealing has been unable to keep pace with ever increasing sizes of designs and FPGA chip resources. Without utilizing information of the circuit topology, it relies on large amounts of random swap operations, which are time-costly. This paper proposes an adaptive range-based algorithm to improve the behavior of swap operations and limit the swap distances by introducing the concept of range-limiting strategy for nets. It avoids unnecessary design space exploration, and thus can converge to near-optimal solutions much more quickly. The experimental results are based on the Titan benchmarks, which contain 4K to 30K blocks, including logic array blocks, inputs and outputs, digital signal processors, and random access memories. This approach achieves <inline-formula> <tex-math notation="LaTeX">2.82\boldsymbol \times </tex-math></inline-formula> speed up, 4.8% reduction on wire length, 4.1% improvement on critical path compared with the SA from VTR with wire length-driven optimization, and <inline-formula> <tex-math notation="LaTeX">1.78\boldsymbol \times </tex-math></inline-formula> speed up, 10% reduction on wire length, 2% reduction on critical path with path timing-driven optimization. It also manifests better scalability on larger benchmarks.