Efficient Coding Architectures for Reed-Solomon and Low-Density Parity-Check Decoders for Magnetic and Other Data Storage Systems

• Published in: IEEE transactions on magnetics Vol. 54; no. 2; pp. 1 - 15
• Main Authors: Mondal, Arijit, Thatimattala, Satyannarayana, Yalamaddi, Vamshi Krishna, Garani, Shayan Srinivasa
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Berlekamp–Massey (BM) algorithm; Codes; Coding; Computer architecture; Data storage; Decoders; Decoding; Delays; Density; Electronic devices; Engine blocks; Error correcting codes; Error correction; error correction codes (ECC); field programmable gate array (FPGA); Field programmable gate arrays; high speed; Kintex-7 FPGA; layered min-sum; low complexity; low latency; low-density parity-check (LDPC); Magnetism; Measurement; Noise levels; non-uniform quantization (NUQ); Parallel processing; Parity; Parity check codes; Polynomials; Rams; Reed–Solomon (RS) decoder; State of the art; Storage systems; Throughput
• ISSN: 0018-9464; 1941-0069
• DOI: 10.1109/TMAG.2017.2778053

High-performance error correction codes are used in high-density data storage devices to overcome noise and channel impairments. In this paper, we develop novel and efficient decoding architectures for Reed-Solomon (RS) and low-density parity-check (LDPC) codes that are used in almost all data storage devices. First, we present a high-speed low-latency hard-decision-based pipelined RS decoder architecture that computes the error locator polynomial in exactly 2t clock cycles without parallelism. The RS decoder is a two-stage pipelined engine operating at the least latency possible, thereby, significantly reducing the size of the delay buffer. The RS decoder is implemented using Cadence tools and Kintex-7 field programmable gate array (FPGA). The technology-scaled normalized throughput of the pipelined RS decoder is almost two times compared with the existing decoders. The overall processing latency is reduced by almost 80% compared with the existing designs. Second, we design a high-throughput LDPC decoder using layered and non-layered min-sum algorithm based on non-uniform quantization (NUQ) on an FPGA kit. Unlike the standard state-of-the-art uniform quantization used in virtually all decoder circuits, our NUQ technique: 1) achieves a slight performance improvement of ~0.1 dB in the signal-to-noise ratio using equal number of bits and 2) yields 20% area savings (using 1 bit less) for the block RAMs used for storing intermediate check node and variable node messages.