APA (7th ed.) Citation

Hsieh, C., & Lin, C. (2024). All-nMOS Power-Rail ESD Clamp Circuit With Compact Area and Low Leakage. IEEE transactions on electron devices, 71(9), 5205-5211. https://doi.org/10.1109/TED.2024.3434776

Chicago Style (17th ed.) Citation

Hsieh, Chia-You, and Chun-Yu Lin. "All-nMOS Power-Rail ESD Clamp Circuit With Compact Area and Low Leakage." IEEE Transactions on Electron Devices 71, no. 9 (2024): 5205-5211. https://doi.org/10.1109/TED.2024.3434776.

MLA (9th ed.) Citation

Hsieh, Chia-You, and Chun-Yu Lin. "All-nMOS Power-Rail ESD Clamp Circuit With Compact Area and Low Leakage." IEEE Transactions on Electron Devices, vol. 71, no. 9, 2024, pp. 5205-5211, https://doi.org/10.1109/TED.2024.3434776.