Synthesizing VHDL from Activity Models in UML 2

• Published in: International journal of circuit theory and applications Vol. 42; no. 5; pp. 542 - 550
• Main Authors: Balderas-Contreras, Tomás, Cumplido, René, Rodríguez, Gustavo
• Format: Journal Article
• Language: English
• Published: Bognor Regis Blackwell Publishing Ltd 01.05.2014; Wiley Subscription Services, Inc
• Subjects: code generation; domain-specific modeling; meta-modeling; model-driven engineering; UML 2; VHDL
• ISSN: 0098-9886; 1097-007X
• DOI: 10.1002/cta.1874

ABSTRACT This document describes a synthesis technology that generates structural VHDL code from models describing the flow of data required to perform algorithms operating on bit‐blocks. The models are built using restricted activity diagrams in the Unified Modeling Language version 2. The code generator is developed using Acceleo, a technology to implement transformations from models to text. The technology described in this paper exploits the principles of object orientation and model‐driven engineering. The primary aim is to improve productivity and alleviate complexity during the design of digital hardware systems that implement demanding operations used by a wide variety of computing devices. The use of the technology is illustrated with the generation of VHDL code from models describing a block cipher algorithm. Copyright © 2012 John Wiley & Sons, Ltd. We explore the feasibility of transforming high‐level models of block cipher algorithms, built using activity diagrams in the Unified Modeling Language version 2 (UML 2), to source code in VHDL. The lower level VHDL representation may be synthesized and implemented in a hardware platform like a FPGA. We describe how to adapt the UML 2 language to model block cipher algorithms accurately and the transformation tool that generates VHDL code from the UML 2 diagrams. This technology aims at improving the productivity of the designers.