Towards High-Performance Bufferless NoCs with SCEPTER

• Published in: IEEE computer architecture letters Vol. 15; no. 1; pp. 62 - 65
• Main Authors: Daya, Bhavya K., Li-Shiuan Peh, Chandrakasan, Anantha P.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Computer architecture; Pipelines; Ports (Computers); Resource management; Routing; Switches; Throughput; on-chip mesh networks; bypassing; deflection routing; Multiprocessor interconnection; bufferless router
• ISSN: 1556-6056; 1556-6064
• DOI: 10.1109/LCA.2015.2428699

In the many-core era, the network on-chip (NoC) is playing a larger role in meeting performance, area and power goals, as router buffers contribute greatly to NoC area and power usage. Proposals have advocated bufferless NoCs, however a performance wall has been reached such that high throughput performance has not been extracted. We present SCEPTER, a high-performance bufferless mesh NoC that sets up single-cycle virtual express paths dynamically across the chip, allowing deflected packets to go through non-minimal paths with no latency penalty. For a 64 node network, we demonstrate an average 62 percent reduction in latency and an average 1.3× higher throughput over a baseline bufferless NoC for synthetic traffic patterns; with comparable performance to a single-cycle multihop buffered mesh network with six flit buffers, per input port, in each router.