CMP Process Optimization Engineering by Machine Learning

• Published in: IEEE transactions on semiconductor manufacturing Vol. 34; no. 3; pp. 280 - 285
• Main Authors: Yu, Hsiang-Meng, Lin, Chih-Chen, Hsu, Min-Hsuan, Chen, Yen-Ting, Chen, Kuang-Wei, Luoh, Tuung, Yang, Ling-Wuu, Yang, Tahone, Chen, Kuang-Chao
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; artificial intelligence; Artificial neural networks; Chemical-mechanical polishing; closed loop systems; Disks; Layout; Layouts; Machine learning; Neural networks; Optimization; Prediction algorithms; Predictive models; Process control; Semiconductor device modeling; Semiconductor process modeling; Slurries; Test vehicles; thickness control; Topology; Wafers
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/TSM.2021.3072361

Advanced Chemical-mechanical polishing (CMP) process not only needs to maintain stable run-to-run thickness control but also achieve better within wafer/within chip planarization performance. Furthermore, slurries or other consumable parts, like PAD and Disks selection are also the keys for CMP process optimization. The most difficult thing in CMP process is to have capability to predict and cover the various topologies and layout densities patterned wafers and preventing the hot spots occurrences. In this study, different Neural-Network algorithm with data pre-processing models are implemented to the in-line CMP CLC tuning and dishing/erosion prediction at various topology/pattern density test vehicle pattern wafers. Transfer learning technique is implemented on the original Neural -Network algorithm model, the behavior of real product can be simulated and predicted based on the knowledge of test vehicle database successfully. With the aid of multiple layer erosion/ dishing Neural-Network algorithm model prediction, the potential high risky hot spots can be highlighted at the initial layout design stage, then further shorten the turn-around time of design layout validation.