Multibeam Digital Array Receiver Using a 16-Point Multiplierless DFT Approximation

• Published in: IEEE transactions on antennas and propagation Vol. 67; no. 2; pp. 925 - 933
• Main Authors: Ariyarathna, Viduneth, Coelho, Diego F. G., Pulipati, Sravan, Cintra, Renato J., Bayer, Fabio M., Dimitrov, V. S., Madanayake, Arjuna
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 5G mobile communication; Algorithms; Antenna arrays; Approximation; Array signal processing; Beamforming; Complexity; Complexity theory; Computation; Discrete Fourier transforms; Discrete transforms; Fast Fourier transformations; Field programmable gate arrays; Fourier transforms; low-complexity algorithms; Mathematical analysis; multibeam; Patch antennas; Power consumption; Radio frequency; Receivers; spatial DFT
• ISSN: 0018-926X; 1558-2221
• DOI: 10.1109/TAP.2018.2882629

An <inline-formula> <tex-math notation="LaTeX">N </tex-math></inline-formula>-element array with receivers subject to an <inline-formula> <tex-math notation="LaTeX">N </tex-math></inline-formula>-point spatial fast Fourier transform (FFT) leads to <inline-formula> <tex-math notation="LaTeX">N </tex-math></inline-formula> directionally orthogonal radio frequency (RF) beams. FFTs are fast algorithms for computing the <inline-formula> <tex-math notation="LaTeX">N </tex-math></inline-formula>-point discrete Fourier transform (DFT) at reduced complexity. The brute-force computation of a DFT requires <inline-formula> <tex-math notation="LaTeX">\mathcal {O}(N^{2}) </tex-math></inline-formula> multiplications while an FFT provides the same computation at <inline-formula> <tex-math notation="LaTeX">\mathcal {O}(N \log N) </tex-math></inline-formula> multiplications. The digital chip area and power consumption of the DFT computation are still dominated by the multipliers required by the FFT used. In this paper, an approximation to the 16-point DFT is proposed which maintains mathematical properties close to the ideal 16-point DFT to obtain 16 RF beams by computing an approximate spatial DFT in every clock cycle at significantly lower area and power in the digital realization. The proposed approximation can be implemented using FFT-like fast algorithms that are multiplierless, thereby further reducing the digital chip area and power consumption associated with multiplication in a conventional FFT approach to zero. A 16-beam beamformer employing a 16-element linear array of patch antennas, direct-conversion receivers, and a Xilinx Virtex-6 field-programmable gate array-based real-time digital back-end clocked at 240 MHz are described as an example realization of 16 complex-valued (IQ) receive-mode RF beams, centered at 2.4 GHz with 120 MHz of bandwidth per beam.